mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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Merge pull request #906 from antonio-nino-diaz-arm/an/asserts-release
Add `ENABLE_ASSERTIONS` build option
This commit is contained in:
davidcunado-arm
GitHub
commit
2edf64827f
27 changed files with 118 additions and 92 deletions
12
Makefile
12
Makefile
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@ -50,10 +50,14 @@ include ${MAKE_HELPERS_DIRECTORY}build_env.mk
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# Default values for build configurations, and their dependencies
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################################################################################
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ifdef ASM_ASSERTION
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$(warning ASM_ASSERTION is removed, use ENABLE_ASSERTIONS instead.)
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endif
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include ${MAKE_HELPERS_DIRECTORY}defaults.mk
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# ASM_ASSERTION enabled for DEBUG builds only
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ASM_ASSERTION := ${DEBUG}
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# Assertions enabled for DEBUG builds by default
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ENABLE_ASSERTIONS := ${DEBUG}
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ENABLE_PMF := ${ENABLE_RUNTIME_INSTRUMENTATION}
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PLAT := ${DEFAULT_PLAT}
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@ -439,13 +443,13 @@ endif
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# Build options checks
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################################################################################
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$(eval $(call assert_boolean,ASM_ASSERTION))
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$(eval $(call assert_boolean,COLD_BOOT_SINGLE_CPU))
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$(eval $(call assert_boolean,CREATE_KEYS))
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$(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS))
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$(eval $(call assert_boolean,CTX_INCLUDE_FPREGS))
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$(eval $(call assert_boolean,DEBUG))
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$(eval $(call assert_boolean,DISABLE_PEDANTIC))
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$(eval $(call assert_boolean,ENABLE_ASSERTIONS))
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$(eval $(call assert_boolean,ENABLE_PLAT_COMPAT))
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$(eval $(call assert_boolean,ENABLE_PMF))
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$(eval $(call assert_boolean,ENABLE_PSCI_STAT))
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@ -478,10 +482,10 @@ $(eval $(call add_define,ARM_CCI_PRODUCT_ID))
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$(eval $(call add_define,ARM_ARCH_MAJOR))
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$(eval $(call add_define,ARM_ARCH_MINOR))
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$(eval $(call add_define,ARM_GIC_ARCH))
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$(eval $(call add_define,ASM_ASSERTION))
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$(eval $(call add_define,COLD_BOOT_SINGLE_CPU))
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$(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS))
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$(eval $(call add_define,CTX_INCLUDE_FPREGS))
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$(eval $(call add_define,ENABLE_ASSERTIONS))
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$(eval $(call add_define,ENABLE_PLAT_COMPAT))
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$(eval $(call add_define,ENABLE_PMF))
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$(eval $(call add_define,ENABLE_PSCI_STAT))
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@ -114,7 +114,7 @@ void bl1_main(void)
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print_errata_status();
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#if DEBUG
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#if ENABLE_ASSERTIONS
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u_register_t val;
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/*
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* Ensure that MMU/Caches and coherency are turned on
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@ -141,7 +141,7 @@ void bl1_main(void)
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assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
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else
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assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
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#endif
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#endif /* ENABLE_ASSERTIONS */
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/* Perform remaining generic architectural setup from EL3 */
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bl1_arch_setup();
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@ -90,7 +90,7 @@ func report_exception
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no_ret plat_panic_handler
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endfunc report_exception
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#if ASM_ASSERTION
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#if ENABLE_ASSERTIONS
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.section .rodata.assert_str, "aS"
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assert_msg1:
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.asciz "ASSERT: File "
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@ -107,6 +107,11 @@ assert_msg2:
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* ---------------------------------------------------------------------------
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*/
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func asm_assert
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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/*
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* Only print the output if LOG_LEVEL is higher or equal to
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* LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
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*/
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/* Stash the parameters already in r0 and r1 */
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mov r5, r0
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mov r6, r1
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@ -147,9 +152,10 @@ dec_print_loop:
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bl plat_crash_console_flush
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1:
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#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
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no_ret plat_panic_handler
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endfunc asm_assert
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#endif
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#endif /* ENABLE_ASSERTIONS */
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/*
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* This function prints a string from address in r4
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@ -41,7 +41,7 @@
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/* The offset to add to get ascii for numerals '0 - 9' */
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#define ASCII_OFFSET_NUM 0x30
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#if ASM_ASSERTION
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#if ENABLE_ASSERTIONS
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.section .rodata.assert_str, "aS"
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assert_msg1:
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.asciz "ASSERT: File "
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@ -78,6 +78,11 @@ dec_print_loop:
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* ---------------------------------------------------------------------------
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*/
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func asm_assert
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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/*
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* Only print the output if LOG_LEVEL is higher or equal to
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* LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
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*/
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mov x5, x0
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mov x6, x1
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/* Ensure the console is initialized */
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@ -98,9 +103,10 @@ func asm_assert
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asm_print_line_dec
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bl plat_crash_console_flush
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_assert_loop:
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#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
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no_ret plat_panic_handler
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endfunc asm_assert
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#endif
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#endif /* ENABLE_ASSERTIONS */
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/*
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* This function prints a string from address in x4.
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@ -203,11 +203,6 @@ performed.
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in MPIDR is set and access the bit-fields in MPIDR accordingly. Default
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value of this flag is 0.
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* `ASM_ASSERTION`: This flag determines whether the assertion checks within
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assembly source files are enabled or not. This option defaults to the
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value of `DEBUG` - that is, by default this is only enabled for a debug
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build of the firmware.
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* `BL2`: This is an optional build option which specifies the path to BL2
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image for the `fip` target. In this case, the BL2 in the ARM Trusted
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Firmware will not be built.
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@ -286,6 +281,14 @@ performed.
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payload. Please refer to the "Booting an EL3 payload" section for more
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details.
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* `ENABLE_ASSERTIONS`: This option controls whether or not calls to `assert()`
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are compiled out. For debug builds, this option defaults to 1, and calls to
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`assert()` are left in place. For release builds, this option defaults to 0
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and calls to `assert()` function are compiled out. This option can be set
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independently of `DEBUG`. It can also be used to hide any auxiliary code
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that is only required for the assertion and does not fit in the assertion
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itself.
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* `ENABLE_PMF`: Boolean option to enable support for optional Performance
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Measurement Framework(PMF). Default is 0.
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@ -39,7 +39,7 @@ static uintptr_t g_cci_base;
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static unsigned int g_max_master_id;
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static const int *g_cci_slave_if_map;
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#if DEBUG
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#if ENABLE_ASSERTIONS
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static int validate_cci_map(const int *map)
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{
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unsigned int valid_cci_map = 0;
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@ -72,7 +72,7 @@ static int validate_cci_map(const int *map)
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return 1;
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}
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#endif /* DEBUG */
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#endif /* ENABLE_ASSERTIONS */
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void cci_init(uintptr_t cci_base,
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const int *map,
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@ -81,7 +81,7 @@ static inline void ccn_reg_write(uintptr_t periphbase,
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mmio_write_64(region_base + register_offset, value);
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}
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#if DEBUG
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#if ENABLE_ASSERTIONS
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typedef struct rn_info {
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unsigned char node_desc[MAX_RN_NODES];
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@ -224,7 +224,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc)
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info.node_desc[node_id]--;
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}
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}
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#endif /* DEBUG */
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#endif /* ENABLE_ASSERTIONS */
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/*******************************************************************************
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* This function validates parameters passed by the platform (in a debug build)
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@ -234,7 +234,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc)
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******************************************************************************/
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void ccn_init(const ccn_desc_t *plat_desc)
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{
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#if DEBUG
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#if ENABLE_ASSERTIONS
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ccn_validate_plat_params(plat_desc);
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#endif
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -33,7 +33,7 @@
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#include <mmio.h>
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#include <stddef.h>
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#include <tzc400.h>
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#include "tzc_common_private.c"
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#include "tzc_common_private.h"
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/*
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* Macros which will be used by common core functions.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -28,6 +28,9 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __TZC_COMMON_PRIVATE_H__
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#define __TZC_COMMON_PRIVATE_H__
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#include <arch.h>
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#include <arch_helpers.h>
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#include <mmio.h>
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@ -190,8 +193,9 @@
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nsaid_permissions); \
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}
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#if DEBUG
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static unsigned int _tzc_read_peripheral_id(uintptr_t base)
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#if ENABLE_ASSERTIONS
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static inline unsigned int _tzc_read_peripheral_id(uintptr_t base)
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{
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unsigned int id;
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@ -203,7 +207,7 @@ static unsigned int _tzc_read_peripheral_id(uintptr_t base)
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}
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#ifdef AARCH32
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static unsigned long long _tzc_get_max_top_addr(int addr_width)
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static inline unsigned long long _tzc_get_max_top_addr(int addr_width)
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{
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/*
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* Assume at least 32 bit wide address and initialize the max.
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@ -232,4 +236,6 @@ static unsigned long long _tzc_get_max_top_addr(int addr_width)
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(UINT64_MAX >> (64 - (addr_width)))
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#endif /* AARCH32 */
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#endif
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#endif /* ENABLE_ASSERTIONS */
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#endif /* __TZC_COMMON_PRIVATE_H__ */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -33,7 +33,7 @@
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#include <mmio.h>
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#include <tzc_dmc500.h>
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#include "tzc_common.h"
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#include "tzc_common_private.c"
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#include "tzc_common_private.h"
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/*
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* Macros which will be used by common core functions.
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@ -257,7 +257,7 @@ void tzc_dmc500_set_action(tzc_action_t action)
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static void validate_plat_driver_data(
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const tzc_dmc500_driver_data_t *plat_driver_data)
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{
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#if DEBUG
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#if ENABLE_ASSERTIONS
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int i;
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unsigned int dmc_id;
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uintptr_t dmc_base;
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@ -273,7 +273,7 @@ static void validate_plat_driver_data(
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dmc_id = _tzc_read_peripheral_id(dmc_base);
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assert(dmc_id == DMC500_PERIPHERAL_ID);
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}
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#endif /* DEBUG */
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#endif /* ENABLE_ASSERTIONS */
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
|
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
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@ -51,8 +51,8 @@ static const io_dev_info_t *devices[MAX_IO_DEVICES];
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/* Number of currently registered devices */
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static unsigned int dev_count;
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#if DEBUG /* Extra validation functions only used in debug builds */
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/* Extra validation functions only used when asserts are enabled */
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#if ENABLE_ASSERTIONS
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/* Return a boolean value indicating whether a device connector is valid */
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static int is_valid_dev_connector(const io_dev_connector_t *dev_con)
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@ -89,7 +89,8 @@ static int is_valid_seek_mode(io_seek_mode_t mode)
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return ((mode != IO_SEEK_INVALID) && (mode < IO_SEEK_MAX));
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}
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#endif /* End of debug-only validation functions */
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#endif /* ENABLE_ASSERTIONS */
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/* End of extra validation functions only used when asserts are enabled */
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/* Open a connection to a specific device */
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|
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@ -148,7 +148,7 @@
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_init_memory, _init_c_runtime, _exception_vectors
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/* Make sure we are in Secure Mode */
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#if ASM_ASSERTION
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCR
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tst r0, #SCR_NS_BIT
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ASM_ASSERT(eq)
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|
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@ -87,7 +87,7 @@ void cm_set_context_by_mpidr(uint64_t mpidr,
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******************************************************************************/
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static inline void cm_set_next_context(void *context)
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{
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#if DEBUG
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#if ENABLE_ASSERTIONS
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uint64_t sp_mode;
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|
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/*
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@ -98,7 +98,7 @@ static inline void cm_set_next_context(void *context)
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: "=r" (sp_mode));
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assert(sp_mode == MODE_SP_EL0);
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#endif
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#endif /* ENABLE_ASSERTIONS */
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__asm__ volatile("msr spsel, #1\n"
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"mov sp, %0\n"
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|
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@ -34,30 +34,27 @@
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* @(#)assert.h 8.2 (Berkeley) 1/21/94
|
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* $FreeBSD$
|
||||
*/
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#include <sys/cdefs.h>
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/*
|
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* Unlike other ANSI header files, <assert.h> may usefully be included
|
||||
* multiple times, with and without NDEBUG defined.
|
||||
* Portions copyright (c) 2017, ARM Limited and Contributors.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#undef assert
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#undef _assert
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||||
|
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#ifdef NDEBUG
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#define assert(e) ((void)0)
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#define _assert(e) ((void)0)
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#else
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#define _assert(e) assert(e)
|
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|
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#define assert(e) ((e) ? (void)0 : __assert(__func__, __FILE__, \
|
||||
__LINE__, #e))
|
||||
#endif /* NDEBUG */
|
||||
|
||||
#ifndef _ASSERT_H_
|
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#define _ASSERT_H_
|
||||
|
||||
#include <sys/cdefs.h>
|
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|
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#if ENABLE_ASSERTIONS
|
||||
#define _assert(e) assert(e)
|
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#define assert(e) ((e) ? (void)0 : __assert(__func__, __FILE__, \
|
||||
__LINE__, #e))
|
||||
#else
|
||||
#define assert(e) ((void)0)
|
||||
#define _assert(e) ((void)0)
|
||||
#endif /* ENABLE_ASSERTIONS */
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|
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__BEGIN_DECLS
|
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void __assert(const char *, const char *, int, const char *) __dead2;
|
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__END_DECLS
|
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|
||||
#endif /* !_ASSERT_H_ */
|
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|
|
|
|||
|
|
@ -162,7 +162,7 @@ endfunc zeromem
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* --------------------------------------------------------------------------
|
||||
*/
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||||
func memcpy4
|
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#if ASM_ASSERTION
|
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#if ENABLE_ASSERTIONS
|
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orr r3, r0, r1
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tst r3, #0x3
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ASM_ASSERT(eq)
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|
|
|
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|
|
@ -215,7 +215,7 @@ func zeromem_dczva
|
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tmp1 .req x4
|
||||
tmp2 .req x5
|
||||
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
/*
|
||||
* Check for M bit (MMU enabled) of the current SCTLR_EL(1|3)
|
||||
* register value and panic if the MMU is disabled.
|
||||
|
|
@ -228,7 +228,7 @@ func zeromem_dczva
|
|||
|
||||
tst tmp1, #SCTLR_M_BIT
|
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ASM_ASSERT(ne)
|
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#endif /* ASM_ASSERTION */
|
||||
#endif /* ENABLE_ASSERTIONS */
|
||||
|
||||
/* stop_address is the address past the last to zero */
|
||||
add stop_address, cursor, length
|
||||
|
|
@ -247,7 +247,7 @@ func zeromem_dczva
|
|||
mov tmp2, #(1 << 2)
|
||||
lsl block_size, tmp2, block_size
|
||||
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
/*
|
||||
* Assumes block size is at least 16 bytes to avoid manual realignment
|
||||
* of the cursor at the end of the DCZVA loop.
|
||||
|
|
@ -444,7 +444,7 @@ endfunc zeromem_dczva
|
|||
* --------------------------------------------------------------------------
|
||||
*/
|
||||
func memcpy16
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
orr x3, x0, x1
|
||||
tst x3, #0xf
|
||||
ASM_ASSERT(eq)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -35,7 +35,7 @@
|
|||
|
||||
func aem_generic_core_pwr_dwn
|
||||
/* Assert if cache is enabled */
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
ldcopr r0, SCTLR
|
||||
tst r0, #SCTLR_C_BIT
|
||||
ASM_ASSERT(eq)
|
||||
|
|
@ -51,7 +51,7 @@ endfunc aem_generic_core_pwr_dwn
|
|||
|
||||
func aem_generic_cluster_pwr_dwn
|
||||
/* Assert if cache is enabled */
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
ldcopr r0, SCTLR
|
||||
tst r0, #SCTLR_C_BIT
|
||||
ASM_ASSERT(eq)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -76,7 +76,7 @@ func cortex_a32_core_pwr_dwn
|
|||
push {r12, lr}
|
||||
|
||||
/* Assert if cache is enabled */
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
ldcopr r0, SCTLR
|
||||
tst r0, #SCTLR_C_BIT
|
||||
ASM_ASSERT(eq)
|
||||
|
|
@ -107,7 +107,7 @@ func cortex_a32_cluster_pwr_dwn
|
|||
push {r12, lr}
|
||||
|
||||
/* Assert if cache is enabled */
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
ldcopr r0, SCTLR
|
||||
tst r0, #SCTLR_C_BIT
|
||||
ASM_ASSERT(eq)
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ func reset_handler
|
|||
/* Get the matching cpu_ops pointer (clobbers: r0 - r5) */
|
||||
bl get_cpu_ops_ptr
|
||||
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
cmp r0, #0
|
||||
ASM_ASSERT(ne)
|
||||
#endif
|
||||
|
|
@ -92,7 +92,7 @@ func prepare_cpu_pwr_dwn
|
|||
pop {r2, lr}
|
||||
|
||||
ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
cmp r0, #0
|
||||
ASM_ASSERT(ne)
|
||||
#endif
|
||||
|
|
@ -118,7 +118,7 @@ func init_cpu_ops
|
|||
cmp r1, #0
|
||||
bne 1f
|
||||
bl get_cpu_ops_ptr
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
cmp r0, #0
|
||||
ASM_ASSERT(ne)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ func reset_handler
|
|||
|
||||
/* Get the matching cpu_ops pointer */
|
||||
bl get_cpu_ops_ptr
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
cmp x0, #0
|
||||
ASM_ASSERT(ne)
|
||||
#endif
|
||||
|
|
@ -94,7 +94,7 @@ func prepare_cpu_pwr_dwn
|
|||
|
||||
mrs x1, tpidr_el3
|
||||
ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
cmp x0, #0
|
||||
ASM_ASSERT(ne)
|
||||
#endif
|
||||
|
|
@ -120,7 +120,7 @@ func init_cpu_ops
|
|||
cbnz x0, 1f
|
||||
mov x10, x30
|
||||
bl get_cpu_ops_ptr
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
cmp x0, #0
|
||||
ASM_ASSERT(ne)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -32,15 +32,18 @@
|
|||
#include <debug.h>
|
||||
#include <platform.h>
|
||||
|
||||
/*
|
||||
* This is a basic implementation. This could be improved.
|
||||
*/
|
||||
void __assert (const char *function, const char *file, unsigned int line,
|
||||
void __assert(const char *function, const char *file, unsigned int line,
|
||||
const char *assertion)
|
||||
{
|
||||
#if LOG_LEVEL >= LOG_LEVEL_INFO
|
||||
/*
|
||||
* Only print the output if LOG_LEVEL is higher or equal to
|
||||
* LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
|
||||
*/
|
||||
tf_printf("ASSERT: %s <%d> : %s\n", function, line, assertion);
|
||||
|
||||
console_flush();
|
||||
#endif
|
||||
|
||||
plat_panic_handler();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -85,13 +85,13 @@
|
|||
static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
|
||||
__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
|
||||
|
||||
#if DEBUG
|
||||
#if ENABLE_ASSERTIONS
|
||||
static unsigned long long get_max_supported_pa(void)
|
||||
{
|
||||
/* Physical address space size for long descriptor format. */
|
||||
return (1ULL << 40) - 1ULL;
|
||||
}
|
||||
#endif
|
||||
#endif /* ENABLE_ASSERTIONS */
|
||||
|
||||
void init_xlat_tables(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@ static unsigned long long calc_physical_addr_size_bits(
|
|||
return TCR_PS_BITS_4GB;
|
||||
}
|
||||
|
||||
#if DEBUG
|
||||
#if ENABLE_ASSERTIONS
|
||||
/* Physical Address ranges supported in the AArch64 Memory Model */
|
||||
static const unsigned int pa_range_bits_arr[] = {
|
||||
PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
|
||||
|
|
@ -144,7 +144,7 @@ static unsigned long long get_max_supported_pa(void)
|
|||
|
||||
return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL;
|
||||
}
|
||||
#endif
|
||||
#endif /* ENABLE_ASSERTIONS */
|
||||
|
||||
void init_xlat_tables(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -109,7 +109,7 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
|
|||
assert((base_pa + (unsigned long long)size - 1ULL) <=
|
||||
(PLAT_PHY_ADDR_SPACE_SIZE - 1));
|
||||
|
||||
#if DEBUG
|
||||
#if ENABLE_ASSERTIONS
|
||||
|
||||
/* Check for PAs and VAs overlaps with all other regions */
|
||||
for (mm = mmap; mm->size; ++mm) {
|
||||
|
|
@ -154,7 +154,7 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
|
|||
|
||||
mm = mmap; /* Restore pointer to the start of the array */
|
||||
|
||||
#endif /* DEBUG */
|
||||
#endif /* ENABLE_ASSERTIONS */
|
||||
|
||||
/* Find correct place in mmap to insert new region */
|
||||
while (mm->base_va < base_va && mm->size)
|
||||
|
|
|
|||
|
|
@ -37,13 +37,13 @@
|
|||
#include <xlat_tables_v2.h>
|
||||
#include "../xlat_tables_private.h"
|
||||
|
||||
#if DEBUG
|
||||
#if ENABLE_ASSERTIONS
|
||||
static unsigned long long xlat_arch_get_max_supported_pa(void)
|
||||
{
|
||||
/* Physical address space size for long descriptor format. */
|
||||
return (1ull << 40) - 1ull;
|
||||
}
|
||||
#endif /* DEBUG*/
|
||||
#endif /* ENABLE_ASSERTIONS*/
|
||||
|
||||
int is_mmu_enabled(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ static unsigned long long calc_physical_addr_size_bits(
|
|||
return TCR_PS_BITS_4GB;
|
||||
}
|
||||
|
||||
#if DEBUG
|
||||
#if ENABLE_ASSERTIONS
|
||||
/* Physical Address ranges supported in the AArch64 Memory Model */
|
||||
static const unsigned int pa_range_bits_arr[] = {
|
||||
PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
|
||||
|
|
@ -94,7 +94,7 @@ unsigned long long xlat_arch_get_max_supported_pa(void)
|
|||
|
||||
return (1ull << pa_range_bits_arr[pa_range]) - 1ull;
|
||||
}
|
||||
#endif /* DEBUG*/
|
||||
#endif /* ENABLE_ASSERTIONS*/
|
||||
|
||||
int is_mmu_enabled(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -131,7 +131,7 @@ endfunc platform_set_stack
|
|||
* -------------------------------------------------------
|
||||
*/
|
||||
func_deprecated platform_get_stack
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
mrs x1, mpidr_el1
|
||||
cmp x0, x1
|
||||
ASM_ASSERT(eq)
|
||||
|
|
@ -150,7 +150,7 @@ endfunc_deprecated platform_get_stack
|
|||
* -----------------------------------------------------
|
||||
*/
|
||||
func_deprecated platform_set_stack
|
||||
#if ASM_ASSERTION
|
||||
#if ENABLE_ASSERTIONS
|
||||
mrs x1, mpidr_el1
|
||||
cmp x0, x1
|
||||
ASM_ASSERT(eq)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue