mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-22 20:38:03 +00:00
Merge changes from topics "ls1088a", "ls1088a-prepare" into integration
* changes: docs(layerscape): add ls1088a soc and board support feat(ls1088aqds): add ls1088aqds board support feat(ls1088ardb): add ls1088ardb board support feat(ls1088a): add new SoC platform ls1088a build(changelog): add new scopes for ls1088a feat(bl2): add support to separate no-loadable sections refactor(layerscape): refine comparison of inerconnection feat(layerscape): add soc helper macro definition for chassis 3 feat(nxp-gic): add some macros definition for gicv3 feat(layerscape): add CHASSIS 3 support for tbbr feat(layerscape): define more chassis 3 hardware address feat(nxp-crypto): add chassis 3 support feat(nxp-dcfg): add Chassis 3 support feat(lx2): enable DDR erratas for lx2 platforms feat(layerscape): print DDR errata information feat(nxp-ddr): add workaround for errata A050958 feat(layerscape): add new soc errata a010539 support feat(layerscape): add new soc errata a009660 support feat(nxp-ddr): add rawcard 1F support fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically fix(nxp-tools): fix create_pbl print log build(changelog): add new scopes for NXP driver
This commit is contained in:
Joanna Farley
TrustedFirmware Code Review
commit
2ea18c7df3
47 changed files with 3596 additions and 56 deletions
2
Makefile
2
Makefile
|
|
@ -1021,6 +1021,7 @@ $(eval $(call assert_booleans,\
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RESET_TO_BL31 \
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SAVE_KEYS \
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SEPARATE_CODE_AND_RODATA \
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SEPARATE_BL2_NOLOAD_REGION \
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SEPARATE_NOBITS_REGION \
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SPIN_ON_BL1_EXIT \
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SPM_MM \
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@ -1136,6 +1137,7 @@ $(eval $(call add_defines,\
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RAS_EXTENSION \
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RESET_TO_BL31 \
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SEPARATE_CODE_AND_RODATA \
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SEPARATE_BL2_NOLOAD_REGION \
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SEPARATE_NOBITS_REGION \
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RECLAIM_INIT_CODE \
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SPD_${SPD} \
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|
|
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -17,6 +17,11 @@ MEMORY {
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RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
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#else
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RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
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#if SEPARATE_BL2_NOLOAD_REGION
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RAM_NOLOAD (rw!a): ORIGIN = BL2_NOLOAD_START, LENGTH = BL2_NOLOAD_LIMIT - BL2_NOLOAD_START
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#else
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#define RAM_NOLOAD RAM
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#endif
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#endif
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}
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@ -106,9 +111,18 @@ SECTIONS
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__DATA_RAM_END__ = __DATA_END__;
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RELA_SECTION >RAM
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STACK_SECTION >RAM
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BSS_SECTION >RAM
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XLAT_TABLE_SECTION >RAM
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#if SEPARATE_BL2_NOLOAD_REGION
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SAVED_ADDR = .;
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. = BL2_NOLOAD_START;
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__BL2_NOLOAD_START__ = .;
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#endif
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STACK_SECTION >RAM_NOLOAD
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BSS_SECTION >RAM_NOLOAD
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XLAT_TABLE_SECTION >RAM_NOLOAD
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#if SEPARATE_BL2_NOLOAD_REGION
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__BL2_NOLOAD_END__ = .;
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. = SAVED_ADDR;
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#endif
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#if USE_COHERENT_MEM
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/*
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@ -349,6 +349,16 @@ subsections:
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- title: LS1046AQDS
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scope: ls1046aqds
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- title: LS1088A
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scope: ls1088a
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subsections:
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- title: LS1088ARDB
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scope: ls1088ardb
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- title: LS1088AQDS
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scope: ls1088aqds
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- title: QEMU
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scope: qemu
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@ -748,6 +758,12 @@ subsections:
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- title: NXP Crypto
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scope: nxp-crypto
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- title: DDR
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scope: nxp-ddr
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- title: GIC
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scope: nxp-gic
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- title: Renesas
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scope: renesas-drivers
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|
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@ -573,6 +573,14 @@ NXP SoC Part LS1046A and its platform port
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:|F|: plat/nxp/soc-ls1046a/ls1046afrwy
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:|F|: plat/nxp/soc-ls1046a/ls1046aqds
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NXP SoC Part LS1088A and its platform port
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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:|M|: Jiafei Pan <jiafei.pan@nxp.com>
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:|G|: `JiafeiPan`_
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:|F|: plat/nxp/soc-ls1088a
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:|F|: plat/nxp/soc-ls1088a/ls1088ardb
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:|F|: plat/nxp/soc-ls1088a/ls1088aqds
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QEMU platform port
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^^^^^^^^^^^^^^^^^^
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:|M|: Jens Wiklander <jens.wiklander@linaro.org>
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|
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@ -647,6 +647,13 @@ Common build options
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``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
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sections are placed in RAM immediately following the loaded firmware image.
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- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the
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NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM
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discontiguous from loaded firmware images. When set, the platform need to
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provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This
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flag is disabled by default and NOLOAD sections are placed in RAM immediately
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following the loaded firmware image.
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- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration
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access requests via a standard SMCCC defined in `DEN0115`_. When combined with
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UEFI+ACPI this can provide a certain amount of OS forward compatibility
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|
@ -961,7 +968,7 @@ Firmware update options
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--------------
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*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
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*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
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.. _DEN0115: https://developer.arm.com/docs/den0115/latest
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.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
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|
|
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@ -103,7 +103,7 @@ line of QorIQ communications processors. Featuring power-efficient 64-bit
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Arm Cortex-A72 cores with ECC-protected L1 and L2 cache memories for high
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reliability, running up to 1.8 GHz.
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Details about LS1043A can be found at `ls1046a`_.
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Details about LS1046A can be found at `ls1046a`_.
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- LS1046ARDB Board:
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@ -113,7 +113,7 @@ architecture processor. The LS1046ARDB board supports the Layerscape LS1046A
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processor and is optimized to support the DDR4 memory and a full complement
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of high-speed SerDes ports.
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Details about LS1043A RDB board can be found at `ls1046ardb`_.
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Details about LS1046A RDB board can be found at `ls1046ardb`_.
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- LS1046AFRWY Board:
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@ -124,7 +124,28 @@ board supports the LS1046A processor, onboard DDR4 memory, multiple Gigabit
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Ethernet, USB3.0 and M2_Type_E interfaces for Wi-Fi, FRWY-LS1046A-AC includes
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the Wi-Fi card.
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Details about LS1043A RDB board can be found at `ls1046afrwy`_.
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Details about LS1046A FRWY board can be found at `ls1046afrwy`_.
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5. LS1088A
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- SoC Overview:
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The LS1088A family of multicore communications processors combines up to and eight
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Arm Cortex-A53 cores with the advanced, high-performance data path and network
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peripheral interfaces required for wireless access points, networking infrastructure,
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intelligent edge access, including virtual customer premise equipment (vCPE) and
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high-performance industrial applications.
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Details about LS1088A can be found at `ls1088a`_.
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- LS1088ARDB Board:
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The LS1088A reference design board provides a comprehensive platform that
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enables design and evaluation of the product (LS1088A processor). This RDB
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comes pre-loaded with a board support package (BSP) based on a standard
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Linux kernel.
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Details about LS1088A RDB board can be found at `ls1088ardb`_.
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Table of supported boot-modes by each platform & platform that needs FIP-DDR:
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-----------------------------------------------------------------------------
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@ -144,6 +165,8 @@ Table of supported boot-modes by each platform & platform that needs FIP-DDR:
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+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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| ls1046afrwy | yes | yes | | | | | | no |
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+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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| ls1088ardb | yes | yes | | | | | | no |
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+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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Boot Sequence
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@ -336,7 +359,7 @@ should be modified based on the binary size of the image to be copied.
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-- Then reset to alternate bank to boot up ATF.
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Command for lx2160a and ls1028a platforms:
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Command for lx2160a, ls1088a and ls1028a platforms:
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.. code:: shell
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@ -370,7 +393,7 @@ should be modified based on the binary size of the image to be copied.
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-- Then reset to sd/emmc to boot up ATF from sd/emmc as boot-source.
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Command for lx2160A and ls1028a platforms:
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Command for lx2160A, ls1088a and ls1028a platforms:
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.. code:: shell
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@ -445,4 +468,6 @@ Refer `nxp-ls-tbbr.rst`_ for detailed user steps.
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.. _ls1046a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1046a-and-1026a-processors:LS1046A
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.. _ls1046ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1046a-reference-design-board:LS1046A-RDB
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.. _ls1046afrwy: https://www.nxp.com/design/qoriq-developer-resources/ls1046a-freeway-board:FRWY-LS1046A
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.. _ls1088a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1088a-and-1048a-processor:LS1088A
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.. _ls1088ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1088a-reference-design-board:LS1088A-RDB
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.. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst
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|
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@ -1,5 +1,5 @@
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/*
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* Copyright 2020-2021 NXP
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* Copyright 2020-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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@ -74,14 +74,11 @@ const devdisr5_info_t *get_devdisr5_info(void)
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reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_DEVDISR5_OFFSET);
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devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
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#if defined(CONFIG_CHASSIS_3_2)
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devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
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devdisr5_info.ddrc2_present = (reg & DISR5_DDRC2_MASK) ? 0 : 1;
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devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
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#elif defined(CONFIG_CHASSIS_2)
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devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
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devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
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#endif
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devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
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devdisr5_info.is_populated = true;
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return (const devdisr5_info_t *) &devdisr5_info;
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|
|
|
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|
|
@ -1,5 +1,5 @@
|
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#
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# Copyright 2021 NXP
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# Copyright 2021-2022 NXP
|
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#
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# SPDX-License-Identifier: BSD-3-Clause
|
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#
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|
|
@ -19,6 +19,10 @@ ifeq (${ERRATA_DDR_A050450}, 1)
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$(eval $(call add_define,ERRATA_DDR_A050450))
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endif
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ifeq (${ERRATA_DDR_A050958}, 1)
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$(eval $(call add_define,ERRATA_DDR_A050958))
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endif
|
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|
||||
endif
|
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|
||||
ifeq ($(PLAT_DDR_PHY), PHY_GEN1)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* Copyright 2021-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
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*
|
||||
|
|
@ -194,7 +194,7 @@ int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm)
|
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case DDR4_SPD_MINI_RDIMM:
|
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case DDR4_SPD_72B_SO_RDIMM:
|
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pdimm->rdimm = 1;
|
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pdimm->rc = spd->mod_section.registered.ref_raw_card & 0x8f;
|
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pdimm->rc = spd->mod_section.registered.ref_raw_card & 0x9f;
|
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if ((spd->mod_section.registered.reg_map & 0x1) != 0) {
|
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pdimm->mirrored_dimm = 1;
|
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}
|
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|
|
@ -223,7 +223,7 @@ int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm)
|
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case DDR4_SPD_72B_SO_UDIMM:
|
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case DDR4_SPD_16B_SO_DIMM:
|
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case DDR4_SPD_32B_SO_DIMM:
|
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pdimm->rc = spd->mod_section.unbuffered.ref_raw_card & 0x8f;
|
||||
pdimm->rc = spd->mod_section.unbuffered.ref_raw_card & 0x9f;
|
||||
if ((spd->mod_section.unbuffered.addr_mapping & 0x1) != 0) {
|
||||
pdimm->mirrored_dimm = 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* Copyright 2021-2022 NXP
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
|
@ -1673,6 +1673,10 @@ static void prog_dq_dqs_rcv_cntrl(uint16_t *phy,
|
|||
int sel_analog_vref = 1;
|
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uint32_t addr;
|
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|
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#ifdef ERRATA_DDR_A050958
|
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gain_curr_adj_defval = 0x1f;
|
||||
#endif
|
||||
|
||||
dq_dqs_rcv_cntrl = gain_curr_adj_defval << csr_gain_curr_adj_lsb |
|
||||
major_mode_dbyte << csr_major_mode_dbyte_lsb |
|
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dfe_ctrl_defval << csr_dfe_ctrl_lsb |
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -398,6 +398,12 @@
|
|||
ldr r1, =__RW_END__
|
||||
sub r1, r1, r0
|
||||
bl inv_dcache_range
|
||||
#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION
|
||||
ldr r0, =__BL2_NOLOAD_START__
|
||||
ldr r1, =__BL2_NOLOAD_END__
|
||||
sub r1, r1, r0
|
||||
bl inv_dcache_range
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -469,6 +469,14 @@
|
|||
sub x1, x1, x0
|
||||
bl inv_dcache_range
|
||||
#endif
|
||||
#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION
|
||||
adrp x0, __BL2_NOLOAD_START__
|
||||
add x0, x0, :lo12:__BL2_NOLOAD_START__
|
||||
adrp x1, __BL2_NOLOAD_END__
|
||||
add x1, x1, :lo12:__BL2_NOLOAD_END__
|
||||
sub x1, x1, x0
|
||||
bl inv_dcache_range
|
||||
#endif
|
||||
#endif
|
||||
adrp x0, __BSS_START__
|
||||
add x0, x0, :lo12:__BSS_START__
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2017-2021 NXP
|
||||
* Copyright 2017-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
/* Job ring 3 is reserved for usage by sec firmware */
|
||||
#define DEFAULT_JR 3
|
||||
|
||||
#if defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_2)
|
||||
#if defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_2)
|
||||
#define CAAM_JR0_OFFSET 0x10000
|
||||
#define CAAM_JR1_OFFSET 0x20000
|
||||
#define CAAM_JR2_OFFSET 0x30000
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
* Copyright 2018-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
|
|
@ -12,7 +12,7 @@
|
|||
|
||||
#if defined(CONFIG_CHASSIS_2)
|
||||
#include <dcfg_lsch2.h>
|
||||
#elif defined(CONFIG_CHASSIS_3_2)
|
||||
#elif defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3)
|
||||
#include <dcfg_lsch3.h>
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* Copyright 2021-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
|
|
@ -21,8 +21,12 @@
|
|||
#define GICD_CTLR_OFFSET 0x0
|
||||
#define GICD_CLR_SPI_SR 0x58
|
||||
#define GICD_IGROUPR_2 0x88
|
||||
#define GICD_ISENABLER_1 0x104
|
||||
#define GICD_ICENABLER_1 0x184
|
||||
#define GICD_ISENABLER_2 0x108
|
||||
#define GICD_ICENABLER_2 0x188
|
||||
#define GICD_ISENABLER_3 0x10c
|
||||
#define GICD_ICENABLER_3 0x18c
|
||||
#define GICD_ICPENDR_2 0x288
|
||||
#define GICD_ICACTIVER_2 0x388
|
||||
#define GICD_IPRIORITYR_22 0x458
|
||||
|
|
@ -69,6 +73,9 @@
|
|||
#define GIC_IRM_SPI89 0x80000000
|
||||
|
||||
#define GICD_IROUTER_VALUE 0x100
|
||||
#define GICD_ISENABLER_1_VALUE 0x10000000
|
||||
#define GICD_ISENABLER_2_VALUE 0x100
|
||||
#define GICD_ISENABLER_3_VALUE 0x20100
|
||||
#define GICR_WAKER_SLEEP_BIT 0x2
|
||||
#define GICR_WAKER_ASLEEP (1 << 2 | 1 << 1)
|
||||
|
||||
|
|
|
|||
|
|
@ -250,6 +250,10 @@ SEPARATE_CODE_AND_RODATA := 0
|
|||
# separate memory region, which may be discontiguous from the rest of BL31.
|
||||
SEPARATE_NOBITS_REGION := 0
|
||||
|
||||
# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory
|
||||
# region, platform Makefile is free to override this value.
|
||||
SEPARATE_BL2_NOLOAD_REGION := 0
|
||||
|
||||
# If the BL31 image initialisation code is recalimed after use for the secondary
|
||||
# cores stack
|
||||
RECLAIM_INIT_CODE := 0
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* Copyright 2021-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
|
|
@ -15,12 +15,13 @@
|
|||
#define NXP_DCSR_ADDR 0x700000000
|
||||
#define NXP_DCSR_SIZE 0x40000000
|
||||
|
||||
/* Flex-SPI controller address */
|
||||
#define NXP_FLEXSPI_ADDR 0x020C0000
|
||||
/* Flex-SPI Flash Start address */
|
||||
#define NXP_FLEXSPI_FLASH_ADDR 0x20000000
|
||||
/* Quad SPI Region #1 base address */
|
||||
#define NXP_QSPI_FLASH_ADDR 0x20000000
|
||||
|
||||
/* MMU 500 soc.c*/
|
||||
/* IFC Region #1 base address */
|
||||
#define NXP_NOR_FLASH_ADDR 0x30000000
|
||||
|
||||
/* MMU 500 */
|
||||
#define NXP_SMMU_ADDR 0x05000000
|
||||
|
||||
#define NXP_SNVS_ADDR 0x01E90000
|
||||
|
|
@ -34,8 +35,12 @@
|
|||
#define NXP_I2C_ADDR 0x02000000
|
||||
#define NXP_ESDHC_ADDR 0x02140000
|
||||
#define NXP_ESDHC2_ADDR 0x02150000
|
||||
#define NXP_UART_ADDR 0x021C0000
|
||||
#define NXP_UART1_ADDR 0x021D0000
|
||||
#ifndef NXP_UART_ADDR
|
||||
#define NXP_UART_ADDR 0x021C0500
|
||||
#endif
|
||||
#ifndef NXP_UART1_ADDR
|
||||
#define NXP_UART1_ADDR 0x021C0600
|
||||
#endif
|
||||
|
||||
#define NXP_GPIO1_ADDR 0x02300000
|
||||
#define NXP_GPIO2_ADDR 0x02310000
|
||||
|
|
@ -50,8 +55,8 @@
|
|||
#define NXP_TIMER_STATUS_ADDR 0x023F0000
|
||||
|
||||
#define NXP_GICD_ADDR 0x06000000
|
||||
#define NXP_GICR_ADDR 0x06200000
|
||||
#define NXP_GICR_SGI_ADDR 0x06210000
|
||||
#define NXP_GICR_ADDR 0x06100000
|
||||
#define NXP_GICR_SGI_ADDR 0x06110000
|
||||
|
||||
#define NXP_CAAM_ADDR 0x08000000
|
||||
|
||||
|
|
@ -61,4 +66,35 @@
|
|||
|
||||
#define NXP_RESET_ADDR 0x01E60000
|
||||
#define NXP_SEC_REGFILE_ADDR 0x01E88000
|
||||
#endif /* SOC_DEFAULT_BASE_ADDR_H */
|
||||
|
||||
#define NXP_RST_ADDR 0x01E88000
|
||||
|
||||
/* DDR memory Map */
|
||||
#define NXP_DDR_ADDR 0x01080000
|
||||
#define NXP_DDR2_ADDR 0x01090000
|
||||
#define NXP_DDR3_ADDR 0x08210000
|
||||
|
||||
/* QuadSPI base address */
|
||||
#define NXP_QSPI_ADDR 0x020C0000
|
||||
/* IFC base address */
|
||||
#define NXP_IFC_ADDR 0x02240000
|
||||
|
||||
/* CCI400 base address */
|
||||
#define NXP_CCI_ADDR 0x04090000
|
||||
|
||||
/* Global Generic Reference Timer base address */
|
||||
#define NXP_TIMER_ADDR 0x023E0000
|
||||
|
||||
/* OCRAM TZPC base address */
|
||||
#define NXP_OCRAM_TZPC_ADDR 0x02200000
|
||||
|
||||
#define NXP_EPU_ADDR 0x700060000
|
||||
|
||||
#define NXP_CCN_ADDR 0x04000000
|
||||
#define NXP_CCN_HNI_ADDR 0x04080000
|
||||
#define NXP_CCN_HN_F_0_ADDR 0x04200000
|
||||
#define NXP_CCN_HN_F_1_ADDR 0x04210000
|
||||
|
||||
#define TPMWAKEMR0_ADDR 0x700123c50
|
||||
|
||||
#endif /* SOC_DEFAULT_BASE_ADDR_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef SOC_DEFAULT_HELPER_MACROS_H
|
||||
#define SOC_DEFAULT_HELPER_MACROS_H
|
||||
|
||||
#ifdef NXP_OCRAM_TZPC_ADDR
|
||||
#define TZPC_BLOCK_SIZE 0x1000
|
||||
#endif
|
||||
|
||||
/* Reset block register offsets */
|
||||
#ifdef NXP_RESET_ADDR
|
||||
|
||||
/* Register Offset */
|
||||
#define RST_RSTCR_OFFSET 0x0
|
||||
#define RST_RSTRQMR1_OFFSET 0x10
|
||||
#define RST_RSTRQSR1_OFFSET 0x18
|
||||
#define BRR_OFFSET 0x60
|
||||
|
||||
/* helper macros */
|
||||
#define RSTRQMR_RPTOE_MASK (1 << 19)
|
||||
#endif /* NXP_RESET_ADDR */
|
||||
|
||||
#define PCIeRC_RN_I_NODE_ID_OFFSET 0x8
|
||||
#define PoS_CONTROL_REG_OFFSET 0x0
|
||||
#define POS_EARLY_WR_COMP_EN 0x20
|
||||
#define HNI_POS_EN 0x01
|
||||
#define POS_TERMINATE_BARRIERS 0x10
|
||||
#define SERIALIZE_DEV_nGnRnE_WRITES 0x200
|
||||
#define ENABLE_ERR_SIGNAL_TO_MN 0x4
|
||||
#define ENABLE_RESERVE_BIT53 0x400
|
||||
#define ENABLE_WUO 0x10
|
||||
|
||||
#define PORT_S0_CTRL_REG_RNI 0x010
|
||||
#define PORT_S1_CTRL_REG_RNI 0x110
|
||||
#define PORT_S2_CTRL_REG_RNI 0x210
|
||||
#define ENABLE_FORCE_RD_QUO 0x20
|
||||
#define QOS_SETTING 0x00FF000C
|
||||
|
||||
/* epu register offsets and values */
|
||||
#define EPU_EPGCR_OFFSET 0x0
|
||||
#define EPU_EPIMCR10_OFFSET 0x128
|
||||
#define EPU_EPCTR10_OFFSET 0xa28
|
||||
#define EPU_EPCCR10_OFFSET 0x828
|
||||
#ifndef EPU_EPCCR10_VAL
|
||||
#define EPU_EPCCR10_VAL 0xb2800000
|
||||
#endif
|
||||
#define EPU_EPIMCR10_VAL 0xba000000
|
||||
#define EPU_EPCTR10_VAL 0x0
|
||||
#define EPU_EPGCR_VAL (1 << 31)
|
||||
|
||||
#ifdef NXP_CCN_ADDR
|
||||
#define NXP_CCN_HN_F_1_ADDR 0x04210000
|
||||
|
||||
#define CCN_HN_F_SAM_NODEID_MASK 0x7f
|
||||
#define CCN_HN_F_SNP_DMN_CTL_OFFSET 0x200
|
||||
#define CCN_HN_F_SNP_DMN_CTL_SET_OFFSET 0x210
|
||||
#define CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET 0x220
|
||||
#define CCN_HN_F_SNP_DMN_CTL_MASK 0x80a00
|
||||
#define CCN_HNF_NODE_COUNT 8
|
||||
#define CCN_HNF_OFFSET 0x10000
|
||||
|
||||
#define SA_AUX_CTRL_REG_OFFSET 0x500
|
||||
#define NUM_HNI_NODE 2
|
||||
#define CCN_HNI_MEMORY_MAP_SIZE 0x10000
|
||||
|
||||
#define PCIeRC_RN_I_NODE_ID_OFFSET 0x8
|
||||
#define PoS_CONTROL_REG_OFFSET 0x0
|
||||
#define POS_EARLY_WR_COMP_EN 0x20
|
||||
#define HNI_POS_EN 0x01
|
||||
#define POS_TERMINATE_BARRIERS 0x10
|
||||
#define SERIALIZE_DEV_nGnRnE_WRITES 0x200
|
||||
#define ENABLE_ERR_SIGNAL_TO_MN 0x4
|
||||
#define ENABLE_RESERVE_BIT53 0x400
|
||||
#define ENABLE_WUO 0x10
|
||||
#endif
|
||||
|
||||
/* reset register bit */
|
||||
#define RSTRQMR_RPTOE_MASK (1 << 19)
|
||||
|
||||
/* secmon register offsets and bitfields */
|
||||
#define SECMON_HPCOMR_OFFSET 0x4
|
||||
#define SECMON_HPCOMR_NPSWAEN 0x80000000
|
||||
|
||||
/* Secure-Register-File register offsets and bit masks */
|
||||
#ifdef NXP_RST_ADDR
|
||||
/* Register Offset */
|
||||
#define CORE_HOLD_OFFSET 0x140
|
||||
#endif
|
||||
|
||||
#define DCFG_SBEESR2_ADDR 0x00100534
|
||||
#define DCFG_MBEESR2_ADDR 0x00100544
|
||||
/* SBEESR and MBEESR bit mask */
|
||||
#define OCRAM_EESR_MASK 0x00000008
|
||||
|
||||
#endif /* SOC_DEFAULT_HELPER_MACROS_H */
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright 2020-2021 NXP
|
||||
# Copyright 2020-2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -11,14 +11,12 @@ $(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
|
|||
$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
|
||||
endif
|
||||
|
||||
ifeq (${INTERCONNECT}, "CCI400")
|
||||
ifneq (${INTERCONNECT},)
|
||||
$(eval $(call add_define,NXP_HAS_${INTERCONNECT}))
|
||||
ifeq (${INTERCONNECT}, CCI400)
|
||||
ICNNCT_ID := 0x420
|
||||
$(eval $(call add_define,ICNNCT_ID))
|
||||
endif
|
||||
|
||||
ifeq (${INTERCONNECT}, "CCN508")
|
||||
$(eval $(call add_define,NXP_HAS_CCN508))
|
||||
endif
|
||||
|
||||
ifneq (${CHASSIS},)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2018-2020 NXP
|
||||
* Copyright 2018-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
|
|
@ -182,7 +182,7 @@ void ls_bl2_el3_plat_arch_setup(void)
|
|||
unsigned int flags = 0U;
|
||||
/* Initialise the IO layer and register platform IO devices */
|
||||
ls_setup_page_tables(
|
||||
#if SEPARATE_RW_AND_NOLOAD
|
||||
#if SEPARATE_BL2_NOLOAD_REGION
|
||||
BL2_START,
|
||||
BL2_LIMIT - BL2_START,
|
||||
#else
|
||||
|
|
@ -289,8 +289,9 @@ void bl2_plat_preload_setup(void)
|
|||
if ((dram_regions_info.region[0].addr == 0)
|
||||
&& (dram_regions_info.total_dram_size > 0)) {
|
||||
populate_dram_regions_info();
|
||||
|
||||
#ifdef PLAT_XLAT_TABLES_DYNAMIC
|
||||
mmap_add_ddr_region_dynamically();
|
||||
#endif
|
||||
}
|
||||
|
||||
/* setup the memory region access permissions */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* Copyright 2021-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
|
|
@ -19,6 +19,15 @@ void soc_errata(void)
|
|||
INFO("SoC workaround for Errata A008850 Early-Phase was applied\n");
|
||||
erratum_a008850_early();
|
||||
#endif
|
||||
#if ERRATA_SOC_A009660
|
||||
INFO("SoC workaround for Errata A009660 was applied\n");
|
||||
erratum_a009660();
|
||||
#endif
|
||||
#if ERRATA_SOC_A010539
|
||||
INFO("SoC workaround for Errata A010539 was applied\n");
|
||||
erratum_a010539();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following DDR Erratas workaround are implemented in DDR driver,
|
||||
* but print information here.
|
||||
|
|
@ -29,4 +38,22 @@ void soc_errata(void)
|
|||
#if ERRATA_DDR_A050450
|
||||
INFO("SoC workaround for DDR Errata A050450 was applied\n");
|
||||
#endif
|
||||
#if ERRATA_DDR_A050958
|
||||
INFO("SoC workaround for DDR Errata A050958 was applied\n");
|
||||
#endif
|
||||
#if ERRATA_DDR_A008511
|
||||
INFO("SoC workaround for DDR Errata A008511 was applied\n");
|
||||
#endif
|
||||
#if ERRATA_DDR_A009803
|
||||
INFO("SoC workaround for DDR Errata A009803 was applied\n");
|
||||
#endif
|
||||
#if ERRATA_DDR_A009942
|
||||
INFO("SoC workaround for DDR Errata A009942 was applied\n");
|
||||
#endif
|
||||
#if ERRATA_DDR_A010165
|
||||
INFO("SoC workaround for DDR Errata A010165 was applied\n");
|
||||
#endif
|
||||
#if ERRATA_DDR_A009663
|
||||
INFO("SoC workaround for DDR Errata A009663 was applied\n");
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright 2021 NXP
|
||||
# Copyright 2021-2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -9,7 +9,9 @@
|
|||
|
||||
ERRATA := \
|
||||
ERRATA_SOC_A050426 \
|
||||
ERRATA_SOC_A008850
|
||||
ERRATA_SOC_A008850 \
|
||||
ERRATA_SOC_A009660 \
|
||||
ERRATA_SOC_A010539
|
||||
|
||||
define enable_errata
|
||||
$(1) ?= 0
|
||||
|
|
|
|||
14
plat/nxp/common/soc_errata/errata_a009660.c
Normal file
14
plat/nxp/common/soc_errata/errata_a009660.c
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include <mmio.h>
|
||||
#include <soc_default_base_addr.h>
|
||||
|
||||
void erratum_a009660(void)
|
||||
{
|
||||
mmio_write_32(NXP_SCFG_ADDR + 0x20c, 0x63b20042);
|
||||
}
|
||||
26
plat/nxp/common/soc_errata/errata_a010539.c
Normal file
26
plat/nxp/common/soc_errata/errata_a010539.c
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include <mmio.h>
|
||||
|
||||
#include <plat_common.h>
|
||||
|
||||
void erratum_a010539(void)
|
||||
{
|
||||
if (get_boot_dev() == BOOT_DEVICE_QSPI) {
|
||||
unsigned int *porsr1 = (void *)(NXP_DCFG_ADDR +
|
||||
DCFG_PORSR1_OFFSET);
|
||||
uint32_t val;
|
||||
|
||||
val = (gur_in32(porsr1) & ~PORSR1_RCW_MASK);
|
||||
mmio_write_32((uint32_t)(NXP_DCSR_DCFG_ADDR +
|
||||
DCFG_DCSR_PORCR1_OFFSET), htobe32(val));
|
||||
/* Erratum need to set '1' to all bits for reserved SCFG register 0x1a8 */
|
||||
mmio_write_32((uint32_t)(NXP_SCFG_ADDR + 0x1a8),
|
||||
htobe32(0xffffffff));
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* Copyright 2021-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
|
|
@ -17,4 +17,12 @@ void erratum_a008850_early(void);
|
|||
void erratum_a008850_post(void);
|
||||
#endif
|
||||
|
||||
#ifdef ERRATA_SOC_A009660
|
||||
void erratum_a009660(void);
|
||||
#endif
|
||||
|
||||
#ifdef ERRATA_SOC_A010539
|
||||
void erratum_a010539(void);
|
||||
#endif
|
||||
|
||||
#endif /* ERRATA_LIST_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright 2020 NXP
|
||||
# Copyright 2020-2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -13,6 +13,12 @@ include $(PLAT_DRIVERS_PATH)/csu/csu.mk
|
|||
CSF_FILE := input_blx_ch${CHASSIS}
|
||||
BL2_CSF_FILE := input_bl2_ch${CHASSIS}
|
||||
else
|
||||
ifeq ($(CHASSIS), 3)
|
||||
CSF_FILE := input_blx_ch${CHASSIS}
|
||||
BL2_CSF_FILE := input_bl2_ch${CHASSIS}
|
||||
PBI_CSF_FILE := input_pbi_ch${CHASSIS}
|
||||
$(eval $(call add_define, CSF_HDR_CH3))
|
||||
else
|
||||
ifeq ($(CHASSIS), 3_2)
|
||||
CSF_FILE := input_blx_ch3
|
||||
BL2_CSF_FILE := input_bl2_ch${CHASSIS}
|
||||
|
|
@ -22,6 +28,7 @@ else
|
|||
$(error -> CHASSIS not set!)
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
PLAT_AUTH_PATH := $(PLAT_DRIVERS_PATH)/auth
|
||||
|
||||
|
|
|
|||
1817
plat/nxp/soc-ls1088a/aarch64/ls1088a.S
Normal file
1817
plat/nxp/soc-ls1088a/aarch64/ls1088a.S
Normal file
File diff suppressed because it is too large
Load diff
69
plat/nxp/soc-ls1088a/aarch64/ls1088a_helpers.S
Normal file
69
plat/nxp/soc-ls1088a/aarch64/ls1088a_helpers.S
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <platform_def.h>
|
||||
|
||||
.globl plat_secondary_cold_boot_setup
|
||||
.globl plat_is_my_cpu_primary
|
||||
.globl plat_reset_handler
|
||||
.globl platform_mem_init
|
||||
|
||||
func platform_mem1_init
|
||||
ret
|
||||
endfunc platform_mem1_init
|
||||
|
||||
func platform_mem_init
|
||||
ret
|
||||
endfunc platform_mem_init
|
||||
|
||||
func apply_platform_errata
|
||||
ret
|
||||
endfunc apply_platform_errata
|
||||
|
||||
func plat_reset_handler
|
||||
mov x29, x30
|
||||
bl apply_platform_errata
|
||||
|
||||
#if defined(IMAGE_BL31)
|
||||
ldr x0, =POLICY_SMMU_PAGESZ_64K
|
||||
cbz x0, 1f
|
||||
/* Set the SMMU page size in the sACR register */
|
||||
bl _set_smmu_pagesz_64
|
||||
#endif
|
||||
1:
|
||||
mov x30, x29
|
||||
ret
|
||||
endfunc plat_reset_handler
|
||||
|
||||
/*
|
||||
* void plat_secondary_cold_boot_setup (void);
|
||||
*
|
||||
* This function performs any platform specific actions
|
||||
* needed for a secondary cpu after a cold reset e.g
|
||||
* mark the cpu's presence, mechanism to place it in a
|
||||
* holding pen etc.
|
||||
*/
|
||||
func plat_secondary_cold_boot_setup
|
||||
/* ls1088a does not do cold boot for secondary CPU */
|
||||
cb_panic:
|
||||
b cb_panic
|
||||
endfunc plat_secondary_cold_boot_setup
|
||||
|
||||
/*
|
||||
* unsigned int plat_is_my_cpu_primary (void);
|
||||
*
|
||||
* Find out whether the current cpu is the primary
|
||||
* cpu.
|
||||
*/
|
||||
func plat_is_my_cpu_primary
|
||||
mrs x0, mpidr_el1
|
||||
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
|
||||
cmp x0, 0x0
|
||||
cset w0, eq
|
||||
ret
|
||||
endfunc plat_is_my_cpu_primary
|
||||
229
plat/nxp/soc-ls1088a/include/soc.h
Normal file
229
plat/nxp/soc-ls1088a/include/soc.h
Normal file
|
|
@ -0,0 +1,229 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SOC_H
|
||||
#define SOC_H
|
||||
|
||||
/* Chassis specific defines - common across SoC's of a particular platform */
|
||||
#include "dcfg_lsch3.h"
|
||||
#include "soc_default_base_addr.h"
|
||||
#include "soc_default_helper_macros.h"
|
||||
|
||||
/*
|
||||
* SVR Definition of LS1088A
|
||||
* A: without security
|
||||
* AE: with security
|
||||
* (not include major and minor rev)
|
||||
*/
|
||||
#define SVR_LS1044A 0x870323
|
||||
#define SVR_LS1044AE 0x870322
|
||||
#define SVR_LS1048A 0x870321
|
||||
#define SVR_LS1048AE 0x870320
|
||||
#define SVR_LS1084A 0x870303
|
||||
#define SVR_LS1084AE 0x870302
|
||||
#define SVR_LS1088A 0x870301
|
||||
#define SVR_LS1088AE 0x870300
|
||||
|
||||
#define SVR_WO_E 0xFFFFFE
|
||||
|
||||
/* Number of cores in platform */
|
||||
#define NUMBER_OF_CLUSTERS 2
|
||||
#define CORES_PER_CLUSTER 4
|
||||
#define PLATFORM_CORE_COUNT (NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER)
|
||||
|
||||
/* set to 0 if the clusters are not symmetrical */
|
||||
#define SYMMETRICAL_CLUSTERS 1
|
||||
|
||||
|
||||
#define NUM_DRAM_REGIONS 2
|
||||
#define NXP_DRAM0_ADDR 0x80000000
|
||||
#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */
|
||||
|
||||
#define NXP_DRAM1_ADDR 0x8080000000
|
||||
#define NXP_DRAM1_MAX_SIZE 0x7F80000000 /* 510 G */
|
||||
|
||||
/* DRAM0 Size defined in platform_def.h */
|
||||
#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
|
||||
|
||||
#define NXP_POWMGTDCR 0x700123C20
|
||||
|
||||
/* epu register offsets and values */
|
||||
#define EPU_EPGCR_OFFSET 0x0
|
||||
#define EPU_EPIMCR10_OFFSET 0x128
|
||||
#define EPU_EPCTR10_OFFSET 0xa28
|
||||
#define EPU_EPCCR10_OFFSET 0x828
|
||||
|
||||
#ifdef EPU_EPCCR10_VAL
|
||||
#undef EPU_EPCCR10_VAL
|
||||
#endif
|
||||
#define EPU_EPCCR10_VAL 0xf2800000
|
||||
|
||||
#define EPU_EPIMCR10_VAL 0xba000000
|
||||
#define EPU_EPCTR10_VAL 0x0
|
||||
#define EPU_EPGCR_VAL (1 << 31)
|
||||
|
||||
/* pmu register offsets and values */
|
||||
#define PMU_PCPW20SR_OFFSET 0x830
|
||||
#define PMU_CLAINACTSETR_OFFSET 0x1100
|
||||
#define PMU_CLAINACTCLRR_OFFSET 0x1104
|
||||
#define PMU_CLSINACTSETR_OFFSET 0x1108
|
||||
#define PMU_CLSINACTCLRR_OFFSET 0x110C
|
||||
#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
|
||||
#define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114
|
||||
#define PMU_CLL2FLUSHSR_OFFSET 0x1118
|
||||
#define PMU_POWMGTCSR_OFFSET 0x4000
|
||||
#define PMU_IPPDEXPCR0_OFFSET 0x4040
|
||||
#define PMU_IPPDEXPCR1_OFFSET 0x4044
|
||||
#define PMU_IPPDEXPCR2_OFFSET 0x4048
|
||||
#define PMU_IPPDEXPCR3_OFFSET 0x404C
|
||||
#define PMU_IPPDEXPCR4_OFFSET 0x4050
|
||||
#define PMU_IPPDEXPCR5_OFFSET 0x4054
|
||||
#define PMU_IPSTPCR0_OFFSET 0x4120
|
||||
#define PMU_IPSTPCR1_OFFSET 0x4124
|
||||
#define PMU_IPSTPCR2_OFFSET 0x4128
|
||||
#define PMU_IPSTPCR3_OFFSET 0x412C
|
||||
#define PMU_IPSTPCR4_OFFSET 0x4130
|
||||
#define PMU_IPSTPCR5_OFFSET 0x4134
|
||||
#define PMU_IPSTPCR6_OFFSET 0x4138
|
||||
#define PMU_IPSTPACK0_OFFSET 0x4140
|
||||
#define PMU_IPSTPACK1_OFFSET 0x4144
|
||||
#define PMU_IPSTPACK2_OFFSET 0x4148
|
||||
#define PMU_IPSTPACK3_OFFSET 0x414C
|
||||
#define PMU_IPSTPACK4_OFFSET 0x4150
|
||||
#define PMU_IPSTPACK5_OFFSET 0x4154
|
||||
#define PMU_IPSTPACK6_OFFSET 0x4158
|
||||
#define PMU_POWMGTCSR_VAL (1 << 20)
|
||||
|
||||
#define IPPDEXPCR0_MASK 0xFFFFFFFF
|
||||
#define IPPDEXPCR1_MASK 0xFFFFFFFF
|
||||
#define IPPDEXPCR2_MASK 0xFFFFFFFF
|
||||
#define IPPDEXPCR3_MASK 0xFFFFFFFF
|
||||
#define IPPDEXPCR4_MASK 0xFFFFFFFF
|
||||
#define IPPDEXPCR5_MASK 0xFFFFFFFF
|
||||
|
||||
/* DEVDISR5_FLX_TMR */
|
||||
#define IPPDEXPCR_FLX_TMR 0x00004000
|
||||
#define DEVDISR5_FLX_TMR 0x00004000
|
||||
|
||||
#define IPSTPCR0_VALUE 0x0041310C
|
||||
#define IPSTPCR1_VALUE 0x000003FF
|
||||
#define IPSTPCR2_VALUE 0x00013006
|
||||
|
||||
/* Dont' stop UART */
|
||||
#define IPSTPCR3_VALUE 0x0000033A
|
||||
|
||||
#define IPSTPCR4_VALUE 0x00103300
|
||||
#define IPSTPCR5_VALUE 0x00000001
|
||||
#define IPSTPCR6_VALUE 0x00000000
|
||||
|
||||
|
||||
#define TZPC_BLOCK_SIZE 0x1000
|
||||
|
||||
/* PORSR1 */
|
||||
#define PORSR1_RCW_MASK 0xFF800000
|
||||
#define PORSR1_RCW_SHIFT 23
|
||||
|
||||
/* CFG_RCW_SRC[6:0] */
|
||||
#define RCW_SRC_TYPE_MASK 0x70
|
||||
|
||||
/* RCW SRC NOR */
|
||||
#define NOR_16B_VAL 0x20
|
||||
|
||||
/*
|
||||
* RCW SRC Serial Flash
|
||||
* 1. SERAIL NOR (QSPI)
|
||||
* 2. OTHERS (SD/MMC, SPI, I2C1)
|
||||
*/
|
||||
#define RCW_SRC_SERIAL_MASK 0x7F
|
||||
#define QSPI_VAL 0x62
|
||||
#define SDHC_VAL 0x40
|
||||
#define EMMC_VAL 0x41
|
||||
|
||||
/*
|
||||
* Required LS standard platform porting definitions
|
||||
* for CCN-504 - Read from RN-F node ID register
|
||||
*/
|
||||
#define PLAT_CLUSTER_TO_CCN_ID_MAP 1, 9, 11, 19
|
||||
|
||||
/* Defines required for using XLAT tables from ARM common code */
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
|
||||
|
||||
/*
|
||||
* Clock Divisors
|
||||
*/
|
||||
#define NXP_PLATFORM_CLK_DIVIDER 1
|
||||
#define NXP_UART_CLK_DIVIDER 2
|
||||
|
||||
/* dcfg register offsets and values */
|
||||
#define DCFG_DEVDISR1_OFFSET 0x70
|
||||
#define DCFG_DEVDISR2_OFFSET 0x74
|
||||
#define DCFG_DEVDISR3_OFFSET 0x78
|
||||
#define DCFG_DEVDISR5_OFFSET 0x80
|
||||
#define DCFG_DEVDISR6_OFFSET 0x84
|
||||
|
||||
#define DCFG_DEVDISR1_SEC (1 << 22)
|
||||
#define DCFG_DEVDISR3_QBMAIN (1 << 12)
|
||||
#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5)
|
||||
#define DCFG_DEVDISR5_MEM (1 << 0)
|
||||
|
||||
#define DEVDISR1_VALUE 0x0041310c
|
||||
#define DEVDISR2_VALUE 0x000003ff
|
||||
#define DEVDISR3_VALUE 0x00013006
|
||||
#define DEVDISR4_VALUE 0x0000033e
|
||||
#define DEVDISR5_VALUE 0x00103300
|
||||
#define DEVDISR6_VALUE 0x00000001
|
||||
|
||||
/*
|
||||
* pwr mgmt features supported in the soc-specific code:
|
||||
* value == 0x0, the soc code does not support this feature
|
||||
* value != 0x0, the soc code supports this feature
|
||||
*/
|
||||
#define SOC_CORE_RELEASE 0x1
|
||||
#define SOC_CORE_RESTART 0x1
|
||||
#define SOC_CORE_OFF 0x1
|
||||
#define SOC_CORE_STANDBY 0x1
|
||||
#define SOC_CORE_PWR_DWN 0x1
|
||||
#define SOC_CLUSTER_STANDBY 0x1
|
||||
#define SOC_CLUSTER_PWR_DWN 0x1
|
||||
#define SOC_SYSTEM_STANDBY 0x1
|
||||
#define SOC_SYSTEM_PWR_DWN 0x1
|
||||
#define SOC_SYSTEM_OFF 0x1
|
||||
#define SOC_SYSTEM_RESET 0x1
|
||||
|
||||
#define SYSTEM_PWR_DOMAINS 1
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
|
||||
NUMBER_OF_CLUSTERS + \
|
||||
SYSTEM_PWR_DOMAINS)
|
||||
|
||||
/* Power state coordination occurs at the system level */
|
||||
#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
|
||||
#define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL
|
||||
|
||||
/* Local power state for power domains in Run state */
|
||||
#define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN
|
||||
|
||||
/* define retention state */
|
||||
#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
|
||||
#define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
|
||||
|
||||
/* define power-down state */
|
||||
#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
|
||||
#define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
/* CCI slave interfaces */
|
||||
static const int cci_map[] = {
|
||||
3,
|
||||
4,
|
||||
};
|
||||
void soc_init_lowlevel(void);
|
||||
void soc_init_percpu(void);
|
||||
void _soc_set_start_addr(unsigned long addr);
|
||||
void _set_platform_security(void);
|
||||
#endif
|
||||
|
||||
#endif /* SOC_H */
|
||||
84
plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c
Normal file
84
plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <ddr.h>
|
||||
#include <utils.h>
|
||||
|
||||
#include <errata.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#ifdef CONFIG_STATIC_DDR
|
||||
#error No static value defined
|
||||
#endif
|
||||
|
||||
static const struct rc_timing rce[] = {
|
||||
{U(1600), U(8), U(8)},
|
||||
{U(1867), U(8), U(8)},
|
||||
{U(2134), U(8), U(9)},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_timing udimm[] = {
|
||||
{U(0x04), rce, U(0x01020307), U(0x08090b06)},
|
||||
};
|
||||
|
||||
int ddr_board_options(struct ddr_info *priv)
|
||||
{
|
||||
int ret;
|
||||
struct memctl_opt *popts = &priv->opt;
|
||||
|
||||
if (popts->rdimm != 0) {
|
||||
debug("RDIMM parameters not set.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm));
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
popts->addr_hash = 1;
|
||||
popts->cpo_sample = U(0x7b);
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
|
||||
DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
|
||||
DDR_CDR2_VREF_TRAIN_EN |
|
||||
DDR_CDR2_VREF_RANGE_2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
long long init_ddr(void)
|
||||
{
|
||||
int spd_addr[] = { NXP_SPD_EEPROM0 };
|
||||
struct ddr_info info;
|
||||
struct sysinfo sys;
|
||||
long long dram_size;
|
||||
|
||||
zeromem(&sys, sizeof(sys));
|
||||
get_clocks(&sys);
|
||||
debug("platform clock %lu\n", sys.freq_platform);
|
||||
debug("DDR PLL %lu\n", sys.freq_ddr_pll0);
|
||||
|
||||
zeromem(&info, sizeof(struct ddr_info));
|
||||
info.num_ctlrs = NUM_OF_DDRC;
|
||||
info.dimm_on_ctlr = DDRC_NUM_DIMM;
|
||||
info.clk = get_ddr_freq(&sys, 0);
|
||||
info.spd_addr = spd_addr;
|
||||
info.ddr[0] = (void *)NXP_DDR_ADDR;
|
||||
|
||||
dram_size = dram_init(&info);
|
||||
if (dram_size < 0) {
|
||||
ERROR("DDR init failed.\n");
|
||||
}
|
||||
|
||||
erratum_a008850_post();
|
||||
|
||||
return dram_size;
|
||||
}
|
||||
81
plat/nxp/soc-ls1088a/ls1088aqds/plat_def.h
Normal file
81
plat/nxp/soc-ls1088a/ls1088aqds/plat_def.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_DEF_H
|
||||
#define PLAT_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
/*
|
||||
* Required without TBBR.
|
||||
* To include the defines for DDR PHY
|
||||
* Images.
|
||||
*/
|
||||
#include <tbbr_img_def.h>
|
||||
|
||||
#include <policy.h>
|
||||
#include <soc.h>
|
||||
|
||||
#define NXP_SPD_EEPROM0 0x51
|
||||
|
||||
#define NXP_SYSCLK_FREQ 100000000
|
||||
#define NXP_DDRCLK_FREQ 100000000
|
||||
|
||||
/* UART related definition */
|
||||
#define NXP_CONSOLE_ADDR NXP_UART_ADDR
|
||||
#define NXP_CONSOLE_BAUDRATE 115200
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#if defined(IMAGE_BL2)
|
||||
#if defined(TRUSTED_BOARD_BOOT)
|
||||
#define PLATFORM_STACK_SIZE 0x2000
|
||||
#else
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
#endif
|
||||
#elif defined(IMAGE_BL31)
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
#endif
|
||||
|
||||
#define BL2_START NXP_OCRAM_ADDR
|
||||
#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
|
||||
#define BL2_NOLOAD_START NXP_OCRAM_ADDR
|
||||
#define BL2_NOLOAD_LIMIT BL2_BASE
|
||||
|
||||
/* IO defines as needed by IO driver framework */
|
||||
#define MAX_IO_DEVICES 4
|
||||
#define MAX_IO_BLOCK_DEVICES 1
|
||||
#define MAX_IO_HANDLES 4
|
||||
|
||||
/*
|
||||
* FIP image defines - Offset at which FIP Image would be present
|
||||
* Image would include Bl31 , Bl33 and Bl32 (optional)
|
||||
*/
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
#define MAX_FIP_DEVICES 2
|
||||
#endif
|
||||
|
||||
#ifndef MAX_FIP_DEVICES
|
||||
#define MAX_FIP_DEVICES 1
|
||||
#endif
|
||||
|
||||
#define BL32_IRQ_SEC_PHY_TIMER 29
|
||||
#define BL31_WDOG_SEC 89
|
||||
|
||||
/*
|
||||
* ID of the secure physical generic timer interrupt used by the BL32.
|
||||
*/
|
||||
#define PLAT_LS_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
|
||||
/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
|
||||
#define PLAT_LS_G0_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
|
||||
|
||||
#endif /* PLAT_DEF_H */
|
||||
28
plat/nxp/soc-ls1088a/ls1088aqds/platform.c
Normal file
28
plat/nxp/soc-ls1088a/ls1088aqds/platform.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat_common.h>
|
||||
|
||||
#pragma weak board_enable_povdd
|
||||
#pragma weak board_disable_povdd
|
||||
|
||||
bool board_enable_povdd(void)
|
||||
{
|
||||
#ifdef CONFIG_POVDD_ENABLE
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
bool board_disable_povdd(void)
|
||||
{
|
||||
#ifdef CONFIG_POVDD_ENABLE
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
31
plat/nxp/soc-ls1088a/ls1088aqds/platform.mk
Normal file
31
plat/nxp/soc-ls1088a/ls1088aqds/platform.mk
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
#
|
||||
# Copyright 2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# board-specific build parameters
|
||||
BOOT_MODE ?= qspi
|
||||
BOARD := ls1088aqds
|
||||
|
||||
# DDR Compilation Configs
|
||||
NUM_OF_DDRC := 1
|
||||
DDRC_NUM_DIMM := 1
|
||||
DDR_ECC_EN := yes
|
||||
|
||||
# On-Board Flash Details
|
||||
QSPI_FLASH_SZ := 0x4000000
|
||||
NOR_FLASH_SZ := 0x20000000
|
||||
|
||||
BL2_SOURCES += ${BOARD_PATH}/ddr_init.c \
|
||||
${BOARD_PATH}/platform.c
|
||||
|
||||
SUPPORTED_BOOT_MODE := qspi \
|
||||
sd \
|
||||
nor
|
||||
|
||||
# Adding platform board build info
|
||||
include plat/nxp/common/plat_make_helper/plat_common_def.mk
|
||||
|
||||
# Adding SoC build info
|
||||
include plat/nxp/soc-ls1088a/soc.mk
|
||||
13
plat/nxp/soc-ls1088a/ls1088aqds/platform_def.h
Normal file
13
plat/nxp/soc-ls1088a/ls1088aqds/platform_def.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <plat_def.h>
|
||||
#include <plat_default_def.h>
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
16
plat/nxp/soc-ls1088a/ls1088aqds/policy.h
Normal file
16
plat/nxp/soc-ls1088a/ls1088aqds/policy.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef POLICY_H
|
||||
#define POLICY_H
|
||||
|
||||
/*
|
||||
* Set this to 0x0 to leave the default SMMU page size in sACR
|
||||
* Set this to 0x1 to change the SMMU page size to 64K
|
||||
*/
|
||||
#define POLICY_SMMU_PAGESZ_64K 0x1
|
||||
|
||||
#endif /* POLICY_H */
|
||||
86
plat/nxp/soc-ls1088a/ls1088ardb/ddr_init.c
Normal file
86
plat/nxp/soc-ls1088a/ls1088ardb/ddr_init.c
Normal file
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <ddr.h>
|
||||
#include <utils.h>
|
||||
|
||||
#include <errata.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#ifdef CONFIG_STATIC_DDR
|
||||
#error No static value defined
|
||||
#endif
|
||||
|
||||
static const struct rc_timing rce[] = {
|
||||
{U(1600), U(8), U(8)},
|
||||
{U(1867), U(8), U(8)},
|
||||
{U(2134), U(8), U(9)},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_timing udimm[] = {
|
||||
{U(0x04), rce, U(0x01030508), U(0x090b0d06)},
|
||||
{U(0x1f), rce, U(0x01030508), U(0x090b0d06)},
|
||||
};
|
||||
|
||||
int ddr_board_options(struct ddr_info *priv)
|
||||
{
|
||||
int ret;
|
||||
struct memctl_opt *popts = &priv->opt;
|
||||
|
||||
if (popts->rdimm != 0) {
|
||||
debug("RDIMM parameters not set.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm));
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
popts->addr_hash = 1;
|
||||
popts->cpo_sample = U(0x7b);
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
|
||||
DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
|
||||
DDR_CDR2_VREF_TRAIN_EN |
|
||||
DDR_CDR2_VREF_RANGE_2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
long long init_ddr(void)
|
||||
{
|
||||
int spd_addr[] = { NXP_SPD_EEPROM0 };
|
||||
struct ddr_info info;
|
||||
struct sysinfo sys;
|
||||
long long dram_size;
|
||||
|
||||
zeromem(&sys, sizeof(sys));
|
||||
get_clocks(&sys);
|
||||
debug("platform clock %lu\n", sys.freq_platform);
|
||||
debug("DDR PLL %lu\n", sys.freq_ddr_pll0);
|
||||
|
||||
zeromem(&info, sizeof(struct ddr_info));
|
||||
info.num_ctlrs = NUM_OF_DDRC;
|
||||
info.dimm_on_ctlr = DDRC_NUM_DIMM;
|
||||
info.clk = get_ddr_freq(&sys, 0);
|
||||
info.spd_addr = spd_addr;
|
||||
info.ddr[0] = (void *)NXP_DDR_ADDR;
|
||||
|
||||
dram_size = dram_init(&info);
|
||||
|
||||
if (dram_size < 0) {
|
||||
ERROR("DDR init failed.\n");
|
||||
}
|
||||
|
||||
erratum_a008850_post();
|
||||
|
||||
return dram_size;
|
||||
}
|
||||
80
plat/nxp/soc-ls1088a/ls1088ardb/plat_def.h
Normal file
80
plat/nxp/soc-ls1088a/ls1088ardb/plat_def.h
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_DEF_H
|
||||
#define PLAT_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
/*
|
||||
* Required without TBBR.
|
||||
* To include the defines for DDR PHY
|
||||
* Images.
|
||||
*/
|
||||
#include <tbbr_img_def.h>
|
||||
|
||||
#include <policy.h>
|
||||
#include <soc.h>
|
||||
|
||||
#define NXP_SPD_EEPROM0 0x51
|
||||
|
||||
#define NXP_SYSCLK_FREQ 100000000
|
||||
#define NXP_DDRCLK_FREQ 100000000
|
||||
|
||||
/* UART related definition */
|
||||
#define NXP_CONSOLE_ADDR NXP_UART_ADDR
|
||||
#define NXP_CONSOLE_BAUDRATE 115200
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#if defined(IMAGE_BL2)
|
||||
#if defined(TRUSTED_BOARD_BOOT)
|
||||
#define PLATFORM_STACK_SIZE 0x2000
|
||||
#else
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
#endif
|
||||
#elif defined(IMAGE_BL31)
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
#endif
|
||||
|
||||
#define BL2_START NXP_OCRAM_ADDR
|
||||
#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
|
||||
#define BL2_NOLOAD_START NXP_OCRAM_ADDR
|
||||
#define BL2_NOLOAD_LIMIT BL2_BASE
|
||||
|
||||
/* IO defines as needed by IO driver framework */
|
||||
#define MAX_IO_DEVICES 4
|
||||
#define MAX_IO_BLOCK_DEVICES 1
|
||||
#define MAX_IO_HANDLES 4
|
||||
|
||||
/*
|
||||
* FIP image defines - Offset at which FIP Image would be present
|
||||
* Image would include Bl31 , Bl33 and Bl32 (optional)
|
||||
*/
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
#define MAX_FIP_DEVICES 2
|
||||
#endif
|
||||
|
||||
#ifndef MAX_FIP_DEVICES
|
||||
#define MAX_FIP_DEVICES 1
|
||||
#endif
|
||||
|
||||
#define BL32_IRQ_SEC_PHY_TIMER 29
|
||||
#define BL31_WDOG_SEC 89
|
||||
|
||||
/*
|
||||
* ID of the secure physical generic timer interrupt used by the BL32.
|
||||
*/
|
||||
#define PLAT_LS_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
|
||||
/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
|
||||
#define PLAT_LS_G0_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
|
||||
#endif /* PLAT_DEF_H */
|
||||
28
plat/nxp/soc-ls1088a/ls1088ardb/platform.c
Normal file
28
plat/nxp/soc-ls1088a/ls1088ardb/platform.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat_common.h>
|
||||
|
||||
#pragma weak board_enable_povdd
|
||||
#pragma weak board_disable_povdd
|
||||
|
||||
bool board_enable_povdd(void)
|
||||
{
|
||||
#ifdef CONFIG_POVDD_ENABLE
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
bool board_disable_povdd(void)
|
||||
{
|
||||
#ifdef CONFIG_POVDD_ENABLE
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
30
plat/nxp/soc-ls1088a/ls1088ardb/platform.mk
Normal file
30
plat/nxp/soc-ls1088a/ls1088ardb/platform.mk
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
#
|
||||
# Copyright 2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# board-specific build parameters
|
||||
BOOT_MODE ?= qspi
|
||||
BOARD := ls1088ardb
|
||||
|
||||
# DDR Compilation Configs
|
||||
NUM_OF_DDRC := 1
|
||||
DDRC_NUM_DIMM := 1
|
||||
DDR_ECC_EN := yes
|
||||
|
||||
# On-Board Flash Details
|
||||
QSPI_FLASH_SZ := 0x4000000
|
||||
|
||||
# Adding Platform files build files
|
||||
BL2_SOURCES += ${BOARD_PATH}/ddr_init.c \
|
||||
${BOARD_PATH}/platform.c
|
||||
|
||||
SUPPORTED_BOOT_MODE := qspi \
|
||||
sd
|
||||
|
||||
# Adding platform board build info
|
||||
include plat/nxp/common/plat_make_helper/plat_common_def.mk
|
||||
|
||||
# Adding SoC build info
|
||||
include plat/nxp/soc-ls1088a/soc.mk
|
||||
13
plat/nxp/soc-ls1088a/ls1088ardb/platform_def.h
Normal file
13
plat/nxp/soc-ls1088a/ls1088ardb/platform_def.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <plat_def.h>
|
||||
#include <plat_default_def.h>
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
15
plat/nxp/soc-ls1088a/ls1088ardb/policy.h
Normal file
15
plat/nxp/soc-ls1088a/ls1088ardb/policy.h
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef POLICY_H
|
||||
#define POLICY_H
|
||||
|
||||
/* Set this to 0x0 to leave the default SMMU page size in sACR
|
||||
* Set this to 0x1 to change the SMMU page size to 64K
|
||||
*/
|
||||
#define POLICY_SMMU_PAGESZ_64K 0x1
|
||||
|
||||
#endif /* POLICY_H */
|
||||
397
plat/nxp/soc-ls1088a/soc.c
Normal file
397
plat/nxp/soc-ls1088a/soc.c
Normal file
|
|
@ -0,0 +1,397 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <caam.h>
|
||||
#include <cci.h>
|
||||
#include <common/debug.h>
|
||||
#include <dcfg.h>
|
||||
#ifdef I2C_INIT
|
||||
#include <i2c.h>
|
||||
#endif
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
#include <ls_interconnect.h>
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
#include <nxp_smmu.h>
|
||||
#endif
|
||||
#include <nxp_timer.h>
|
||||
#include <plat_console.h>
|
||||
#include <plat_gic.h>
|
||||
#include <plat_tzc400.h>
|
||||
#include <pmu.h>
|
||||
#if defined(NXP_SFP_ENABLED)
|
||||
#include <sfp.h>
|
||||
#endif
|
||||
|
||||
#include <errata.h>
|
||||
#ifdef CONFIG_OCRAM_ECC_EN
|
||||
#include <ocram.h>
|
||||
#endif
|
||||
#include <plat_common.h>
|
||||
#include <platform_def.h>
|
||||
#include <soc.h>
|
||||
|
||||
static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2];
|
||||
static struct soc_type soc_list[] = {
|
||||
SOC_ENTRY(LS1044A, LS1044A, 1, 4),
|
||||
SOC_ENTRY(LS1044AE, LS1044AE, 1, 4),
|
||||
SOC_ENTRY(LS1048A, LS1048A, 1, 4),
|
||||
SOC_ENTRY(LS1048AE, LS1048AE, 1, 4),
|
||||
SOC_ENTRY(LS1084A, LS1084A, 2, 4),
|
||||
SOC_ENTRY(LS1084AE, LS1084AE, 2, 4),
|
||||
SOC_ENTRY(LS1088A, LS1088A, 2, 4),
|
||||
SOC_ENTRY(LS1088AE, LS1088AE, 2, 4),
|
||||
};
|
||||
|
||||
static dcfg_init_info_t dcfg_init_data = {
|
||||
.g_nxp_dcfg_addr = NXP_DCFG_ADDR,
|
||||
.nxp_sysclk_freq = NXP_SYSCLK_FREQ,
|
||||
.nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
|
||||
.nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
|
||||
};
|
||||
|
||||
/*
|
||||
* This function dynamically constructs the topology according to
|
||||
* SoC Flavor and returns it.
|
||||
*/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
unsigned int i;
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
|
||||
/*
|
||||
* The highest level is the system level. The next level is constituted
|
||||
* by clusters and then cores in clusters.
|
||||
*/
|
||||
_power_domain_tree_desc[0] = 1;
|
||||
_power_domain_tree_desc[1] = num_clusters;
|
||||
|
||||
for (i = 0; i < _power_domain_tree_desc[1]; i++) {
|
||||
_power_domain_tree_desc[i + 2] = cores_per_cluster;
|
||||
}
|
||||
|
||||
|
||||
return _power_domain_tree_desc;
|
||||
}
|
||||
|
||||
CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
|
||||
assert_invalid_ls1088a_cluster_count);
|
||||
|
||||
/*
|
||||
* This function returns the core count within the cluster corresponding to
|
||||
* `mpidr`.
|
||||
*/
|
||||
unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
|
||||
{
|
||||
return CORES_PER_CLUSTER;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function returns the total number of cores in the SoC
|
||||
*/
|
||||
unsigned int get_tot_num_cores(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
|
||||
return (num_clusters * cores_per_cluster);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function returns the PMU IDLE Cluster mask.
|
||||
*/
|
||||
unsigned int get_pmu_idle_cluster_mask(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
|
||||
return ((1 << num_clusters) - 2);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function returns the PMU Flush Cluster mask.
|
||||
*/
|
||||
unsigned int get_pmu_flush_cluster_mask(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
|
||||
return ((1 << num_clusters) - 2);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function returns the PMU IDLE Core mask.
|
||||
*/
|
||||
unsigned int get_pmu_idle_core_mask(void)
|
||||
{
|
||||
return ((1 << get_tot_num_cores()) - 2);
|
||||
}
|
||||
|
||||
#ifdef IMAGE_BL2
|
||||
|
||||
void soc_bl2_prepare_exit(void)
|
||||
{
|
||||
#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
|
||||
set_sfp_wr_disable();
|
||||
#endif
|
||||
}
|
||||
|
||||
void soc_preload_setup(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* This function returns the boot device based on RCW_SRC
|
||||
*/
|
||||
enum boot_device get_boot_dev(void)
|
||||
{
|
||||
enum boot_device src = BOOT_DEVICE_NONE;
|
||||
uint32_t porsr1;
|
||||
uint32_t rcw_src, val;
|
||||
|
||||
porsr1 = read_reg_porsr1();
|
||||
|
||||
rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
|
||||
|
||||
/* RCW SRC NOR */
|
||||
val = rcw_src & RCW_SRC_TYPE_MASK;
|
||||
if (val == NOR_16B_VAL) {
|
||||
src = BOOT_DEVICE_IFC_NOR;
|
||||
INFO("RCW BOOT SRC is IFC NOR\n");
|
||||
} else {
|
||||
val = rcw_src & RCW_SRC_SERIAL_MASK;
|
||||
switch (val) {
|
||||
case QSPI_VAL:
|
||||
src = BOOT_DEVICE_QSPI;
|
||||
INFO("RCW BOOT SRC is QSPI\n");
|
||||
break;
|
||||
case SDHC_VAL:
|
||||
src = BOOT_DEVICE_EMMC;
|
||||
INFO("RCW BOOT SRC is SD/EMMC\n");
|
||||
break;
|
||||
case EMMC_VAL:
|
||||
src = BOOT_DEVICE_EMMC;
|
||||
INFO("RCW BOOT SRC is SD/EMMC\n");
|
||||
break;
|
||||
default:
|
||||
src = BOOT_DEVICE_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
return src;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function sets up access permissions on memory regions
|
||||
*/
|
||||
void soc_mem_access(void)
|
||||
{
|
||||
dram_regions_info_t *info_dram_regions = get_dram_regions_info();
|
||||
int i = 0;
|
||||
struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
|
||||
int dram_idx, index = 1;
|
||||
|
||||
for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions;
|
||||
dram_idx++) {
|
||||
if (info_dram_regions->region[i].size == 0) {
|
||||
ERROR("DDR init failure, or");
|
||||
ERROR("DRAM regions not populated correctly.\n");
|
||||
break;
|
||||
}
|
||||
|
||||
index = populate_tzc400_reg_list(tzc400_reg_list,
|
||||
dram_idx, index,
|
||||
info_dram_regions->region[dram_idx].addr,
|
||||
info_dram_regions->region[dram_idx].size,
|
||||
NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
|
||||
}
|
||||
|
||||
mem_access_setup(NXP_TZC_ADDR, index,
|
||||
tzc400_reg_list);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function implements soc specific erratum
|
||||
* This is called before DDR is initialized or MMU is enabled
|
||||
*/
|
||||
void soc_early_init(void)
|
||||
{
|
||||
enum boot_device dev;
|
||||
dram_regions_info_t *dram_regions_info = get_dram_regions_info();
|
||||
|
||||
#ifdef CONFIG_OCRAM_ECC_EN
|
||||
ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
|
||||
#endif
|
||||
dcfg_init(&dcfg_init_data);
|
||||
#if LOG_LEVEL > 0
|
||||
/* Initialize the console to provide early debug support */
|
||||
plat_console_init(NXP_CONSOLE_ADDR,
|
||||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
|
||||
#endif
|
||||
enable_timer_base_to_cluster(NXP_PMU_ADDR);
|
||||
enable_core_tb(NXP_PMU_ADDR);
|
||||
|
||||
/*
|
||||
* Use the region(NXP_SD_BLOCK_BUF_ADDR + NXP_SD_BLOCK_BUF_SIZE)
|
||||
* as dma of sd
|
||||
*/
|
||||
dev = get_boot_dev();
|
||||
if (dev == BOOT_DEVICE_EMMC) {
|
||||
mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR,
|
||||
NXP_SD_BLOCK_BUF_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_NS);
|
||||
}
|
||||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
uint32_t mode;
|
||||
|
||||
sfp_init(NXP_SFP_ADDR);
|
||||
/*
|
||||
* For secure boot disable SMMU.
|
||||
* Later when platform security policy comes in picture,
|
||||
* this might get modified based on the policy
|
||||
*/
|
||||
if (check_boot_mode_secure(&mode) == true) {
|
||||
bypass_smmu(NXP_SMMU_ADDR);
|
||||
}
|
||||
|
||||
/*
|
||||
* For Mbedtls currently crypto is not supported via CAAM
|
||||
* enable it when that support is there. In tbbr.mk
|
||||
* the CAAM_INTEG is set as 0.
|
||||
*/
|
||||
#ifndef MBEDTLS_X509
|
||||
/* Initialize the crypto accelerator if enabled */
|
||||
if (is_sec_enabled() == false) {
|
||||
INFO("SEC is disabled.\n");
|
||||
} else {
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
soc_errata();
|
||||
|
||||
delay_timer_init(NXP_TIMER_ADDR);
|
||||
i2c_init(NXP_I2C_ADDR);
|
||||
dram_regions_info->total_dram_size = init_ddr();
|
||||
}
|
||||
#else /* !IMAGE_BL2 */
|
||||
|
||||
void soc_early_platform_setup2(void)
|
||||
{
|
||||
dcfg_init(&dcfg_init_data);
|
||||
/*
|
||||
* Initialize system level generic timer for Socs
|
||||
*/
|
||||
delay_timer_init(NXP_TIMER_ADDR);
|
||||
|
||||
#if LOG_LEVEL > 0
|
||||
/* Initialize the console to provide early debug support */
|
||||
plat_console_init(NXP_CONSOLE_ADDR,
|
||||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
|
||||
#endif
|
||||
}
|
||||
|
||||
void soc_platform_setup(void)
|
||||
{
|
||||
/* Initialize the GIC driver, cpu and distributor interfaces */
|
||||
static uintptr_t target_mask_array[PLATFORM_CORE_COUNT];
|
||||
static interrupt_prop_t ls_interrupt_props[] = {
|
||||
PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S),
|
||||
PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0)
|
||||
};
|
||||
|
||||
plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR,
|
||||
PLATFORM_CORE_COUNT,
|
||||
ls_interrupt_props,
|
||||
ARRAY_SIZE(ls_interrupt_props),
|
||||
target_mask_array,
|
||||
plat_core_pos);
|
||||
|
||||
plat_ls_gic_init();
|
||||
enable_init_timer();
|
||||
}
|
||||
|
||||
/*
|
||||
* This function initializes the soc from the BL31 module
|
||||
*/
|
||||
void soc_init(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
/* low-level init of the soc */
|
||||
soc_init_lowlevel();
|
||||
_init_global_data();
|
||||
soc_init_percpu();
|
||||
_initialize_psci();
|
||||
|
||||
/*
|
||||
* Initialize Interconnect for this cluster during cold boot.
|
||||
* No need for locks as no other CPU is active.
|
||||
*/
|
||||
cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
|
||||
|
||||
/*
|
||||
* Enable Interconnect coherency for the primary CPU's cluster.
|
||||
*/
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
plat_ls_interconnect_enter_coherency(num_clusters);
|
||||
|
||||
/* set platform security policies */
|
||||
_set_platform_security();
|
||||
|
||||
/* Initialize the crypto accelerator if enabled */
|
||||
if (is_sec_enabled() == false) {
|
||||
INFO("SEC is disabled.\n");
|
||||
} else {
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
}
|
||||
}
|
||||
|
||||
void soc_runtime_setup(void)
|
||||
{
|
||||
|
||||
}
|
||||
#endif /* IMAGE_BL2 */
|
||||
|
||||
/*
|
||||
* Function to return the SoC SYS CLK
|
||||
*/
|
||||
unsigned int get_sys_clk(void)
|
||||
{
|
||||
return NXP_SYSCLK_FREQ;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function returns the base counter frequency
|
||||
* after reading the first entry at CNTFID0 (0x20 offset).
|
||||
*
|
||||
* Function is used by:
|
||||
* 1. ARM common code for PSCI management.
|
||||
* 2. ARM Generic Timer init.
|
||||
*/
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
unsigned int counter_base_frequency;
|
||||
/*
|
||||
* Below register specifies the base frequency of the system counter.
|
||||
* As per NXP Board Manuals:
|
||||
* The system counter always works with SYS_REF_CLK/4 frequency clock.
|
||||
*/
|
||||
counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF);
|
||||
|
||||
return counter_base_frequency;
|
||||
}
|
||||
87
plat/nxp/soc-ls1088a/soc.def
Normal file
87
plat/nxp/soc-ls1088a/soc.def
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
#
|
||||
# Copyright 2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# This file contains the basic architecture definitions that drive the build
|
||||
#
|
||||
# -----------------------------------------------------------------------------
|
||||
|
||||
CORE_TYPE := a53
|
||||
|
||||
CACHE_LINE := 6
|
||||
|
||||
# Set to GIC400 or GIC500
|
||||
GIC := GIC500
|
||||
|
||||
# Set to CCI400 or CCN504 or CCN508
|
||||
INTERCONNECT := CCI400
|
||||
|
||||
# Select the DDR PHY generation to be used
|
||||
PLAT_DDR_PHY := PHY_GEN1
|
||||
|
||||
PHYS_SYS := 64
|
||||
|
||||
# Indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
|
||||
CHASSIS := 3
|
||||
|
||||
# TZC IP Details TZC used is TZC380 or TZC400
|
||||
TZC_ID := TZC400
|
||||
|
||||
# CONSOLE Details available is NS16550 or PL011
|
||||
CONSOLE := NS16550
|
||||
|
||||
NXP_SFP_VER := 3_4
|
||||
|
||||
# In IMAGE_BL2, compile time flag for handling Cache coherency
|
||||
# with CAAM for BL2 running from OCRAM
|
||||
SEC_MEM_NON_COHERENT := yes
|
||||
|
||||
|
||||
# OCRAM MAP for BL2
|
||||
# Before BL2
|
||||
# 0x18000000 - 0x18009fff -> Used by ROM code, (TBD - can it be used for xlat tables)
|
||||
# 0x1800a000 - 0x1801Cfff -> Reserved for BL2 binary (76 KB)
|
||||
# 0x1801D000 - 0x1801ffff -> CSF header for BL2 (12 KB)
|
||||
OCRAM_START_ADDR := 0x18000000
|
||||
OCRAM_SIZE := 0x20000
|
||||
|
||||
CSF_HDR_SZ := 0x3000
|
||||
|
||||
# Area of OCRAM reserved by ROM code
|
||||
NXP_ROM_RSVD := 0xa000
|
||||
|
||||
# Input to CST create_hdr_isbc tool
|
||||
BL2_HDR_LOC := 0x1801D000
|
||||
|
||||
# Location of BL2 on OCRAM
|
||||
# BL2_BASE=OCRAM_START_ADDR+NXP_ROM_RSVD
|
||||
BL2_BASE := 0x1800a000
|
||||
|
||||
# SoC ERRATUM to be enabled
|
||||
ERRATA_SOC_A008850 := 1
|
||||
|
||||
# ARM Erratum
|
||||
ERRATA_A53_855873 := 1
|
||||
|
||||
# DDR Erratum
|
||||
ERRATA_DDR_A008511 := 1
|
||||
ERRATA_DDR_A009803 := 1
|
||||
ERRATA_DDR_A009942 := 1
|
||||
ERRATA_DDR_A010165 := 1
|
||||
|
||||
# Define Endianness of each module
|
||||
NXP_ESDHC_ENDIANNESS := LE
|
||||
NXP_SFP_ENDIANNESS := LE
|
||||
NXP_GPIO_ENDIANNESS := LE
|
||||
NXP_SNVS_ENDIANNESS := LE
|
||||
NXP_GUR_ENDIANNESS := LE
|
||||
NXP_SEC_ENDIANNESS := LE
|
||||
NXP_DDR_ENDIANNESS := LE
|
||||
NXP_QSPI_ENDIANNESS := LE
|
||||
|
||||
# OCRAM ECC Enabled
|
||||
OCRAM_ECC_EN := yes
|
||||
110
plat/nxp/soc-ls1088a/soc.mk
Normal file
110
plat/nxp/soc-ls1088a/soc.mk
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
#
|
||||
# Copyright 2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# SoC-specific build parameters
|
||||
SOC := ls1088a
|
||||
PLAT_PATH := plat/nxp
|
||||
PLAT_COMMON_PATH:= plat/nxp/common
|
||||
PLAT_DRIVERS_PATH:= drivers/nxp
|
||||
PLAT_SOC_PATH := ${PLAT_PATH}/soc-${SOC}
|
||||
BOARD_PATH := ${PLAT_SOC_PATH}/${BOARD}
|
||||
|
||||
# Separate BL2 NOLOAD region (.bss, stack, page tables). need to
|
||||
# define BL2_NOLOAD_START and BL2_NOLOAD_LIMIT
|
||||
SEPARATE_BL2_NOLOAD_REGION := 1
|
||||
|
||||
# get SoC-specific defnitions
|
||||
include ${PLAT_SOC_PATH}/soc.def
|
||||
include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk
|
||||
include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
|
||||
|
||||
# For Security Features
|
||||
DISABLE_FUSE_WRITE := 1
|
||||
ifeq (${TRUSTED_BOARD_BOOT}, 1)
|
||||
ifeq (${GENERATE_COT},1)
|
||||
# Save Keys to be used by DDR FIP image
|
||||
SAVE_KEYS=1
|
||||
endif
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
|
||||
# Used by create_pbl tool to
|
||||
# create bl2_<boot_mode>_sec.pbl image
|
||||
SECURE_BOOT := yes
|
||||
endif
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM))
|
||||
|
||||
# Selecting Drivers for SoC
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
|
||||
|
||||
# Selecting PSCI & SIP_SVC support
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31))
|
||||
|
||||
|
||||
# Adding SoC specific files
|
||||
include ${PLAT_COMMON_PATH}/soc_errata/errata.mk
|
||||
|
||||
PLAT_INCLUDES += -I${PLAT_COMMON_PATH}/include/default\
|
||||
-I${BOARD_PATH}\
|
||||
-I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
|
||||
-I${PLAT_COMMON_PATH}/soc_errata\
|
||||
-I${PLAT_COMMON_PATH}/include\
|
||||
-I${PLAT_SOC_PATH}/include
|
||||
|
||||
ifeq (${SECURE_BOOT},yes)
|
||||
include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk
|
||||
endif
|
||||
|
||||
ifeq (${PSCI_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/psci/psci.mk
|
||||
endif
|
||||
|
||||
ifeq (${SIPSVC_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk
|
||||
endif
|
||||
|
||||
# for fuse-fip & fuse-programming
|
||||
ifeq (${FUSE_PROG}, 1)
|
||||
include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk
|
||||
endif
|
||||
|
||||
ifeq (${IMG_LOADR_NEEDED},yes)
|
||||
include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk
|
||||
endif
|
||||
|
||||
# Adding source files for the above selected drivers.
|
||||
include ${PLAT_DRIVERS_PATH}/drivers.mk
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += ${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
|
||||
${PLAT_SOC_PATH}/${ARCH}/${SOC}_helpers.S\
|
||||
${PLAT_SOC_PATH}/soc.c
|
||||
|
||||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
|
||||
${PSCI_SOURCES}\
|
||||
${SIPSVC_SOURCES}\
|
||||
${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S
|
||||
|
||||
ifeq (${TEST_BL31}, 1)
|
||||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S \
|
||||
${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S
|
||||
endif
|
||||
|
||||
BL2_SOURCES += ${DDR_CNTLR_SOURCES}\
|
||||
${TBBR_SOURCES}\
|
||||
${FUSE_SOURCES}
|
||||
|
||||
# Adding TFA setup files
|
||||
include ${PLAT_PATH}/common/setup/common.mk
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
|
||||
# Copyright 2017-2020 NXP Semiconductors
|
||||
# Copyright 2017-2022 NXP Semiconductors
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -107,5 +107,10 @@ ERRATA_A72_859971 := 1
|
|||
# SoC Errata
|
||||
ERRATA_SOC_A050426 := 1
|
||||
|
||||
# DDR Errata
|
||||
ERRATA_DDR_A011396 := 1
|
||||
ERRATA_DDR_A050450 := 1
|
||||
ERRATA_DDR_A050958 := 1
|
||||
|
||||
# enable dynamic memory mapping
|
||||
PLAT_XLAT_TABLES_DYNAMIC := 1
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
* Copyright 2021-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
|
|
@ -507,7 +507,9 @@ int add_boot_ptr_cmd(FILE *fp_rcw_pbi_op)
|
|||
}
|
||||
}
|
||||
|
||||
printf("\nBoot Location Pointer= %x\n", BYTE_SWAP_32(pblimg.ep));
|
||||
printf("\nBoot Location Pointer= 0x%x\n",
|
||||
pblimg.chassis == CHASSIS_2 ? BYTE_SWAP_32(pblimg.ep) :
|
||||
pblimg.ep);
|
||||
ret = SUCCESS;
|
||||
|
||||
bootptr_err:
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright 2018-2020 NXP
|
||||
# Copyright 2018-2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -63,7 +63,7 @@ else
|
|||
-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -f ${BL2_SRC_OFFSET};
|
||||
|
||||
# Append the bl2.bin to the RCW image
|
||||
@echo "bl2_loc is ${bl2_offset}"
|
||||
@echo "bl2_loc is ${bl2_loc} KB"
|
||||
dd if=${BUILD_PLAT}/bl2.bin of=${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl bs=1K seek=${bl2_loc}
|
||||
|
||||
cd ${CREATE_PBL_TOOL_PATH}; ${MAKE} clean ; cd -;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue