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fdts: stm32mp1: move FDCAN to PLL4_R

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LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.

This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.

Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58
This commit is contained in:
Antonio Borneo 2019-07-29 14:46:16 +02:00 • committed by Yann Gautier
parent 57f4b6f839
commit 2dc9fe70da
3 changed files with 3 additions and 3 deletions
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2
fdts/stm32mp157a-avenger96.dts
View file

@ -246,7 +246,7 @@
CLK_UART6_HSI CLK_UART6_HSI
CLK_UART78_HSI CLK_UART78_HSI
CLK_SPDIF_PLL4P CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4Q CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q CLK_SAI3_PLL3Q

2
fdts/stm32mp157a-dk1.dts
View file

@ -266,7 +266,7 @@
CLK_UART6_HSI CLK_UART6_HSI
CLK_UART78_HSI CLK_UART78_HSI
CLK_SPDIF_PLL4P CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4Q CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q CLK_SAI3_PLL3Q

2
fdts/stm32mp157c-ed1.dts
View file

@ -272,7 +272,7 @@
CLK_UART6_HSI CLK_UART6_HSI
CLK_UART78_HSI CLK_UART78_HSI
CLK_SPDIF_PLL4P CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4Q CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q CLK_SAI3_PLL3Q