Merge "fix(ras): trap "RAS error record" accesses only for NS" into integration

This commit is contained in:
Manish Pandey 2022-09-30 14:14:26 +02:00 committed by TrustedFirmware Code Review
commit 2c16b802cb
5 changed files with 18 additions and 15 deletions

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@ -1051,7 +1051,7 @@ $(eval $(call assert_booleans,\
ENCRYPT_BL31 \ ENCRYPT_BL31 \
ENCRYPT_BL32 \ ENCRYPT_BL32 \
ERRATA_SPECULATIVE_AT \ ERRATA_SPECULATIVE_AT \
RAS_TRAP_LOWER_EL_ERR_ACCESS \ RAS_TRAP_NS_ERR_REC_ACCESS \
COT_DESC_IN_DTB \ COT_DESC_IN_DTB \
USE_SP804_TIMER \ USE_SP804_TIMER \
PSA_FWU_SUPPORT \ PSA_FWU_SUPPORT \
@ -1191,7 +1191,7 @@ $(eval $(call add_defines,\
BL2_INV_DCACHE \ BL2_INV_DCACHE \
USE_SPINLOCK_CAS \ USE_SPINLOCK_CAS \
ERRATA_SPECULATIVE_AT \ ERRATA_SPECULATIVE_AT \
RAS_TRAP_LOWER_EL_ERR_ACCESS \ RAS_TRAP_NS_ERR_REC_ACCESS \
COT_DESC_IN_DTB \ COT_DESC_IN_DTB \
USE_SP804_TIMER \ USE_SP804_TIMER \
ENABLE_FEAT_RNG \ ENABLE_FEAT_RNG \

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@ -30,8 +30,8 @@ introduced by the RAS extensions.
The build option ``RAS_EXTENSION`` when set to ``1`` includes the RAS in run The build option ``RAS_EXTENSION`` when set to ``1`` includes the RAS in run
time firmware; ``EL3_EXCEPTION_HANDLING`` and ``HANDLE_EA_EL3_FIRST`` must also time firmware; ``EL3_EXCEPTION_HANDLING`` and ``HANDLE_EA_EL3_FIRST`` must also
be set ``1``. ``RAS_TRAP_LOWER_EL_ERR_ACCESS`` controls the access to the RAS be set ``1``. ``RAS_TRAP_NS_ERR_REC_ACCESS`` controls the access to the RAS
error record registers from lower ELs. error record registers from Non-secure.
.. _ras-figure: .. _ras-figure:

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@ -987,7 +987,7 @@ Common build options
implement this workaround due to the behaviour of the errata mentioned implement this workaround due to the behaviour of the errata mentioned
in new SDEN document which will get published soon. in new SDEN document which will get published soon.
- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR - ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR
bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
This flag is disabled by default. This flag is disabled by default.

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@ -206,6 +206,17 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *
/* Allow access to Allocation Tags when MTE is implemented. */ /* Allow access to Allocation Tags when MTE is implemented. */
scr_el3 |= SCR_ATA_BIT; scr_el3 |= SCR_ATA_BIT;
#if RAS_TRAP_NS_ERR_REC_ACCESS
/*
* SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
* and RAS ERX registers from EL1 and EL2(from any security state)
* are trapped to EL3.
* Set here to trap only for NS EL1/EL2
*
*/
scr_el3 |= SCR_TERR_BIT;
#endif
#ifdef IMAGE_BL31 #ifdef IMAGE_BL31
/* /*
* SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
@ -306,14 +317,6 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e
scr_el3 |= SCR_TRNDR_BIT; scr_el3 |= SCR_TRNDR_BIT;
#endif #endif
#if RAS_TRAP_LOWER_EL_ERR_ACCESS
/*
* SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
* and RAS ERX registers from EL1 and EL2 are trapped to EL3.
*/
scr_el3 |= SCR_TERR_BIT;
#endif
#if !HANDLE_EA_EL3_FIRST #if !HANDLE_EA_EL3_FIRST
/* /*
* SCR_EL3.EA: Do not route External Abort and SError Interrupt External * SCR_EL3.EA: Do not route External Abort and SError Interrupt External

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@ -413,8 +413,8 @@ SUPPORT_STACK_MEMTAG := no
# Select workaround for AT speculative behaviour. # Select workaround for AT speculative behaviour.
ERRATA_SPECULATIVE_AT := 0 ERRATA_SPECULATIVE_AT := 0
# Trap RAS error record access from lower EL # Trap RAS error record access from Non secure
RAS_TRAP_LOWER_EL_ERR_ACCESS := 0 RAS_TRAP_NS_ERR_REC_ACCESS := 0
# Build option to create cot descriptors using fconf # Build option to create cot descriptors using fconf
COT_DESC_IN_DTB := 0 COT_DESC_IN_DTB := 0