From e578702f71f99f728ca2406a89c1345132f44b78 Mon Sep 17 00:00:00 2001 From: Guangjie Song Date: Thu, 31 Oct 2024 21:16:09 +0800 Subject: [PATCH 1/2] feat(mt8196): add DCM driver DCM means dynamic clock management, and it can dynamically slow down or gate clocks during CPU or bus idle. Add MCUSYS or bus related DCM drivers. Enable MCUSYS or bus related DCM by default. Signed-off-by: Guangjie Song Change-Id: I40fc21f5808962ca46870a2f3b9963dc8088f877 --- plat/mediatek/mt8196/drivers/dcm/mtk_dcm.c | 117 +++ .../mt8196/drivers/dcm/mtk_dcm_utils.c | 708 ++++++++++++++++++ .../mt8196/drivers/dcm/mtk_dcm_utils.h | 256 +++++++ plat/mediatek/mt8196/platform.mk | 3 + 4 files changed, 1084 insertions(+) create mode 100644 plat/mediatek/mt8196/drivers/dcm/mtk_dcm.c create mode 100644 plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.c create mode 100644 plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.h diff --git a/plat/mediatek/mt8196/drivers/dcm/mtk_dcm.c b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm.c new file mode 100644 index 000000000..862894857 --- /dev/null +++ b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2025, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +static void dcm_infra(bool on) +{ + dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm(on); + dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm(on); + dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm(on); + dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm(on); +} + +static void dcm_mcusys(bool on) +{ + dcm_mcusys_par_wrap_mcu_misc_dcm(on); +} + +static void dcm_mcusys_acp(bool on) +{ + dcm_mcusys_par_wrap_mcu_acp_dcm(on); +} + +static void dcm_mcusys_adb(bool on) +{ + dcm_mcusys_par_wrap_mcu_adb_dcm(on); +} + +static void dcm_mcusys_apb(bool on) +{ + dcm_mcusys_par_wrap_mcu_apb_dcm(on); +} + +static void dcm_mcusys_bus(bool on) +{ + dcm_mcusys_par_wrap_mcu_bus_qdcm(on); +} + +static void dcm_mcusys_cbip(bool on) +{ + dcm_mcusys_par_wrap_mcu_cbip_dcm(on); +} + +static void dcm_mcusys_chi_mon(bool on) +{ + dcm_mcusys_par_wrap_mcu_chi_mon_dcm(on); +} + +static void dcm_mcusys_core(bool on) +{ + dcm_mcusys_par_wrap_mcu_core_qdcm(on); +} + +static void dcm_mcusys_dsu_acp(bool on) +{ + dcm_mcusys_par_wrap_mcu_dsu_acp_dcm(on); +} + +static void dcm_mcusys_ebg(bool on) +{ + dcm_mcusys_par_wrap_mcu_ebg_dcm(on); +} + +static void dcm_mcusys_gic_spi(bool on) +{ + dcm_mcusys_par_wrap_mcu_gic_spi_dcm(on); +} + +static void dcm_mcusys_io(bool on) +{ + dcm_mcusys_par_wrap_mcu_io_dcm(on); +} + +static void dcm_mcusys_l3c(bool on) +{ + dcm_mcusys_par_wrap_mcu_l3c_dcm(on); +} + +static void dcm_mcusys_stall(bool on) +{ + dcm_mcusys_par_wrap_mcu_stalldcm(on); +} + +static void dcm_vlp(bool on) +{ + dcm_vlp_ao_bcrm_vlp_bus_dcm(on); +} + +int mtk_dcm_init(void) +{ + dcm_infra(true); + dcm_mcusys(true); + dcm_mcusys_acp(true); + dcm_mcusys_adb(true); + dcm_mcusys_apb(true); + dcm_mcusys_bus(true); + dcm_mcusys_cbip(true); + dcm_mcusys_chi_mon(true); + dcm_mcusys_core(true); + dcm_mcusys_dsu_acp(true); + dcm_mcusys_ebg(true); + dcm_mcusys_gic_spi(true); + dcm_mcusys_io(true); + dcm_mcusys_l3c(true); + dcm_mcusys_stall(true); + dcm_vlp(true); + + return 0; +} + +MTK_PLAT_SETUP_0_INIT(mtk_dcm_init); diff --git a/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.c b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.c new file mode 100644 index 000000000..d63755384 --- /dev/null +++ b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.c @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2025, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +static const mmap_region_t dcm_mmap[] = { + MAP_REGION_FLAT(MCUSYS_PAR_WRAP_BASE, MCUSYS_PAR_WRAP_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APINFRA_IO_CTRL_AO, APINFRA_IO_CTRL_AO_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APINFRA_IO_NOC_AO, APINFRA_IO_NOC_AO_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APINFRA_MEM_INTF_NOC_AO, APINFRA_MEM_INTF_NOC_AO_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APINFRA_MEM_CTRL_AO, APINFRA_MEM_CTRL_AO_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(PERI_AO_BCRM_BASE, PERI_AO_BCRM_BASE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(VLP_AO_BCRM_BASE, VLP_AO_BCRM_BASE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; +DECLARE_MTK_MMAP_REGIONS(dcm_mmap); + +static bool dcm_check_state(uintptr_t addr, unsigned int mask, unsigned int state) +{ + return ((mmio_read_32(addr) & mask) == state); +} + +bool dcm_mcusys_par_wrap_mcu_l3c_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_L3_SHARE_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_l3c_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_L3_SHARE_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_L3_SHARE_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_acp_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_MP_ADB_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_ON); + +} + +void dcm_mcusys_par_wrap_mcu_acp_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP_ADB_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP_ADB_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_adb_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_ADB_FIFO_DCM_EN, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_adb_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ADB_FIFO_DCM_EN, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ADB_FIFO_DCM_EN, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_stalldcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_ON); + +} + +void dcm_mcusys_par_wrap_mcu_stalldcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_apb_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_apb_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP0_DCM_CFG0, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_io_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_L3GIC_ARCH_CG_CONFIG, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_ON); + + return ret; +} + +void dcm_mcusys_par_wrap_mcu_io_dcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_L3GIC_ARCH_CG_CONFIG, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_ON); + } else { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_L3GIC_ARCH_CG_CONFIG, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_OFF); + } +} + +bool dcm_mcusys_par_wrap_mcu_bus_qdcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_QDCM_CONFIG1, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_ON); + + return ret; +} + +void dcm_mcusys_par_wrap_mcu_bus_qdcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG1, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_ON); + } else { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG0, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG1, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_OFF); + } +} + +bool dcm_mcusys_par_wrap_mcu_core_qdcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MCUSYS_PAR_WRAP_QDCM_CONFIG2, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_QDCM_CONFIG3, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_ON); + + return ret; +} + +void dcm_mcusys_par_wrap_mcu_core_qdcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG2, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG3, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_ON); + } else { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG2, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_QDCM_CONFIG3, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_OFF); + } +} + +bool dcm_mcusys_par_wrap_mcu_bkr_ldcm1_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_ON); + +} + +void dcm_mcusys_par_wrap_mcu_bkr_ldcm1(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_bkr_ldcm2_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_ON); + +} + +void dcm_mcusys_par_wrap_mcu_bkr_ldcm2(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CI700_DCM_CTRL, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_cbip_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_3TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_4TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO5_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_P2P_CONFIG0, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_L3GIC_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_ON); + ret &= dcm_check_state(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_INFRA_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_ON); + + return ret; +} + +void dcm_mcusys_par_wrap_mcu_cbip_dcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_3TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_4TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO5_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_P2P_CONFIG0, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_L3GIC_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_ON); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_INFRA_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_ON); + } else { + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_3TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO1_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_4TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO5_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_P2P_CONFIG0, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_L3GIC_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_OFF); + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_INFRA_CONFIG, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_MASK, + MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_OFF); + } +} + +bool dcm_mcusys_par_wrap_mcu_misc_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_MP_CENTRAL_FABRIC_SUB_CHANNEL_CG, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_misc_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP_CENTRAL_FABRIC_SUB_CHANNEL_CG, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_MP_CENTRAL_FABRIC_SUB_CHANNEL_CG, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_dsu_acp_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_dsu_acp_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_chi_mon_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_chi_mon_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_gic_spi_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_GIC_SPI_SLOW_CK_CFG, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_gic_spi_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_GIC_SPI_SLOW_CK_CFG, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_GIC_SPI_SLOW_CK_CFG, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_OFF); +} + +bool dcm_mcusys_par_wrap_mcu_ebg_dcm_is_on(void) +{ + return dcm_check_state(MCUSYS_PAR_WRAP_EBG_CKE_WRAP_FIFO_CFG, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_ON); +} + +void dcm_mcusys_par_wrap_mcu_ebg_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_EBG_CKE_WRAP_FIFO_CFG, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_ON); + else + mmio_clrsetbits_32(MCUSYS_PAR_WRAP_EBG_CKE_WRAP_FIFO_CFG, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_MASK, + MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_OFF); +} + +bool dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm_is_on(void) +{ + return dcm_check_state(CLK_AXI_VDNR_DCM_TOP_APINFRA_IO_INTX_BUS_CTRL_0, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_ON); +} + +void dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(CLK_AXI_VDNR_DCM_TOP_APINFRA_IO_INTX_BUS_CTRL_0, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_ON); + else + mmio_clrsetbits_32(CLK_AXI_VDNR_DCM_TOP_APINFRA_IO_INTX_BUS_CTRL_0, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_OFF); +} + +bool dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm_is_on(void) +{ + return dcm_check_state(CLK_IO_NOC_VDNR_DCM_TOP_APINFRA_IO_INTF_PAR_BUS_CTRL_0, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_ON); +} + +void dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(CLK_IO_NOC_VDNR_DCM_TOP_APINFRA_IO_INTF_PAR_BUS_CTRL_0, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_ON); + else + mmio_clrsetbits_32(CLK_IO_NOC_VDNR_DCM_TOP_APINFRA_IO_INTF_PAR_BUS_CTRL_0, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_OFF); +} + +bool dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm_is_on(void) +{ + return dcm_check_state(VDNR_DCM_TOP_APINFRA_MEM_INTF_PAR_BUS_CTRL_0, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_ON); +} + +void dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(VDNR_DCM_TOP_APINFRA_MEM_INTF_PAR_BUS_CTRL_0, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_ON); + else + mmio_clrsetbits_32(VDNR_DCM_TOP_APINFRA_MEM_INTF_PAR_BUS_CTRL_0, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_OFF); +} + +bool dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(CLK_FMEM_SUB_CFG_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_1, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_2, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_3, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_4, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_ON); + ret &= dcm_check_state(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_5, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_ON); + + return ret; +} + +void dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(CLK_FMEM_SUB_CFG_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_1, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_2, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_3, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_4, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_ON); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_5, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_ON); + } else { + mmio_clrsetbits_32(CLK_FMEM_SUB_CFG_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_1, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_2, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_3, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_4, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_OFF); + mmio_clrsetbits_32(CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_5, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_MASK, + APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_OFF); + } +} + +bool dcm_peri_ao_bcrm_peri_bus1_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON); + + return ret; +} + +void dcm_peri_ao_bcrm_peri_bus1_dcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON); + } else { + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_OFF); + } +} + +bool dcm_peri_ao_bcrm_peri_bus2_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON); + ret &= dcm_check_state(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON); + + return ret; +} + +void dcm_peri_ao_bcrm_peri_bus2_dcm(bool on) +{ + if (on) { + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON); + } else { + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_0, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG0_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_1, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG1_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_2, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG2_OFF); + mmio_clrsetbits_32(VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_3, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK, + PERI_AO_BCRM_PERI_BUS_DCM_REG3_OFF); + } +} + +bool dcm_vlp_ao_bcrm_vlp_bus_dcm_is_on(void) +{ + return dcm_check_state(VDNR_DCM_TOP_VLP_PAR_BUS_TOP_CTRL_0, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_MASK, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_ON); +} + +void dcm_vlp_ao_bcrm_vlp_bus_dcm(bool on) +{ + if (on) + mmio_clrsetbits_32(VDNR_DCM_TOP_VLP_PAR_BUS_TOP_CTRL_0, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_MASK, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_ON); + else + mmio_clrsetbits_32(VDNR_DCM_TOP_VLP_PAR_BUS_TOP_CTRL_0, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_MASK, + VLP_AO_BCRM_VLP_BUS_DCM_REG0_OFF); +} diff --git a/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.h b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.h new file mode 100644 index 000000000..3d7a60c28 --- /dev/null +++ b/plat/mediatek/mt8196/drivers/dcm/mtk_dcm_utils.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2025, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DCM_MTK_DCM_UTILS_H_ +#define DCM_MTK_DCM_UTILS_H_ + +#include + +#include + +#define MCUSYS_PAR_WRAP_BASE (MCUCFG_BASE + 0x001B0000) +#define MCUSYS_PAR_WRAP_SIZE (0x10000) +#define APINFRA_IO_CTRL_AO (IO_PHYS + 0x00156000) +#define APINFRA_IO_CTRL_AO_SIZE (0x1000) +#define APINFRA_IO_NOC_AO (IO_PHYS + 0x04012000) +#define APINFRA_IO_NOC_AO_SIZE (0x1000) +#define APINFRA_MEM_INTF_NOC_AO (IO_PHYS + 0x04032000) +#define APINFRA_MEM_INTF_NOC_AO_SIZE (0x1000) +#define APINFRA_MEM_CTRL_AO (IO_PHYS + 0x04124000) +#define APINFRA_MEM_CTRL_AO_SIZE (0x1000) +#define PERI_AO_BCRM_BASE (IO_PHYS + 0x06610000) +#define PERI_AO_BCRM_BASE_SIZE (0x1000) +#define VLP_AO_BCRM_BASE (IO_PHYS + 0x0c030000) +#define VLP_AO_BCRM_BASE_SIZE (0x1000) + +#define MCUSYS_PAR_WRAP_L3_SHARE_DCM_CTRL (MCUSYS_PAR_WRAP_BASE + 0x78) +#define MCUSYS_PAR_WRAP_MP_ADB_DCM_CFG0 (MCUSYS_PAR_WRAP_BASE + 0x270) +#define MCUSYS_PAR_WRAP_ADB_FIFO_DCM_EN (MCUSYS_PAR_WRAP_BASE + 0x278) +#define MCUSYS_PAR_WRAP_MP0_DCM_CFG0 (MCUSYS_PAR_WRAP_BASE + 0x27c) +#define MCUSYS_PAR_WRAP_QDCM_CONFIG0 (MCUSYS_PAR_WRAP_BASE + 0x280) +#define MCUSYS_PAR_WRAP_L3GIC_ARCH_CG_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x294) +#define MCUSYS_PAR_WRAP_QDCM_CONFIG1 (MCUSYS_PAR_WRAP_BASE + 0x284) +#define MCUSYS_PAR_WRAP_QDCM_CONFIG2 (MCUSYS_PAR_WRAP_BASE + 0x288) +#define MCUSYS_PAR_WRAP_QDCM_CONFIG3 (MCUSYS_PAR_WRAP_BASE + 0x28c) +#define MCUSYS_PAR_WRAP_CI700_DCM_CTRL (MCUSYS_PAR_WRAP_BASE + 0x298) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_3TO1_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2a0) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO1_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2a4) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_4TO2_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2a8) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2ac) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_2TO5_CONFIG (MCUSYS_PAR_WRAP_BASE + 0x2b0) +#define MCUSYS_PAR_WRAP_CBIP_P2P_CONFIG0 (MCUSYS_PAR_WRAP_BASE + 0x2b4) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_L3GIC_CONFIG \ + (MCUSYS_PAR_WRAP_BASE + 0x2bc) +#define MCUSYS_PAR_WRAP_CBIP_CABGEN_1TO2_INFRA_CONFIG \ + (MCUSYS_PAR_WRAP_BASE + 0x2c4) +#define MCUSYS_PAR_WRAP_MP_CENTRAL_FABRIC_SUB_CHANNEL_CG \ + (MCUSYS_PAR_WRAP_BASE + 0x2b8) +#define MCUSYS_PAR_WRAP_ACP_SLAVE_DCM_EN (MCUSYS_PAR_WRAP_BASE + 0x2dc) +#define MCUSYS_PAR_WRAP_GIC_SPI_SLOW_CK_CFG (MCUSYS_PAR_WRAP_BASE + 0x2e0) +#define MCUSYS_PAR_WRAP_EBG_CKE_WRAP_FIFO_CFG (MCUSYS_PAR_WRAP_BASE + 0x404) +#define CLK_AXI_VDNR_DCM_TOP_APINFRA_IO_INTX_BUS_CTRL_0 \ + (APINFRA_IO_CTRL_AO + 0x8) +#define CLK_IO_NOC_VDNR_DCM_TOP_APINFRA_IO_INTF_PAR_BUS_CTRL_0 \ + (APINFRA_IO_NOC_AO + 0x4) +#define VDNR_DCM_TOP_APINFRA_MEM_INTF_PAR_BUS_CTRL_0 \ + (APINFRA_MEM_INTF_NOC_AO + 0x0) +#define CLK_FMEM_SUB_CFG_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0 \ + (APINFRA_MEM_CTRL_AO + 0xc) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_0 \ + (APINFRA_MEM_CTRL_AO + 0x14) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_1 \ + (APINFRA_MEM_CTRL_AO + 0x18) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_2 \ + (APINFRA_MEM_CTRL_AO + 0x1c) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_3 \ + (APINFRA_MEM_CTRL_AO + 0x20) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_4 \ + (APINFRA_MEM_CTRL_AO + 0x24) +#define CLK_FMEM_SUB_VDNR_DCM_TOP_APINFRA_MEM_INTX_BUS_CTRL_5 \ + (APINFRA_MEM_CTRL_AO + 0x28) + +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_0 (PERI_AO_BCRM_BASE + 0x2c) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_1 (PERI_AO_BCRM_BASE + 0x30) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_2 (PERI_AO_BCRM_BASE + 0x34) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL1_3 (PERI_AO_BCRM_BASE + 0x38) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_0 (PERI_AO_BCRM_BASE + 0x20) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_1 (PERI_AO_BCRM_BASE + 0x24) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_2 (PERI_AO_BCRM_BASE + 0x28) +#define VDNR_DCM_TOP_PERI_PAR_BUS_CTRL2_3 (PERI_AO_BCRM_BASE + 0x2c) +#define VDNR_DCM_TOP_VLP_PAR_BUS_TOP_CTRL_0 (VLP_AO_BCRM_BASE + 0x5c) + +#define MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_ON 0x1 +#define MCUSYS_PAR_WRAP_MCU_L3C_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_MASK 0x10001 +#define MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_ON 0x10001 +#define MCUSYS_PAR_WRAP_MCU_ACP_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_MASK 0x1FFF07FF +#define MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_ON 0x1FFF07FF +#define MCUSYS_PAR_WRAP_MCU_ADB_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_MASK 0xFF +#define MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_ON 0xFF +#define MCUSYS_PAR_WRAP_MCU_STALLDCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_MASK 0x1FFFF00 +#define MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_ON 0x1FFFF00 +#define MCUSYS_PAR_WRAP_MCU_APB_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_MASK 0x1001 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_ON 0x1001 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_ON 0x1 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_IO_DCM_REG1_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_MASK 0x1110000 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_MASK 0x1111 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_ON 0x1110000 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_ON 0x1111 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_BUS_QDCM_REG1_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_MASK 0x11111111 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_MASK 0x1111 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_ON 0x11111111 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_ON 0x1111 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_CORE_QDCM_REG1_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_MASK 0XFFFF0003 +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_ON 0x8A080002 +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM1_REG0_OFF 0x8A080000 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_MASK 0x3 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_MASK 0x7 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_ON 0x7 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG0_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG1_OFF 0x3 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG2_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG3_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG4_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG5_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG6_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_CBIP_DCM_REG7_OFF 0x1 +#define MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_ON 0x1 +#define MCUSYS_PAR_WRAP_MCU_MISC_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_ON 0x1 +#define MCUSYS_PAR_WRAP_MCU_DSU_ACP_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_MASK 0x1E +#define MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_ON 0 +#define MCUSYS_PAR_WRAP_MCU_CHI_MON_DCM_REG0_OFF 0x1E +#define MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_MASK 0x1 +#define MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_ON 0x1 +#define MCUSYS_PAR_WRAP_MCU_GIC_SPI_DCM_REG0_OFF 0 +#define MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_MASK BIT(2) +#define MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_ON 0 +#define MCUSYS_PAR_WRAP_MCU_EBG_DCM_REG0_OFF BIT(2) +#define APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_MASK 0x14 +#define APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_ON 0x14 +#define APINFRA_IO_CTRL_AO_INFRA_BUS_DCM_REG0_OFF 0 +#define APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_MASK BIT(4) +#define APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_ON BIT(4) +#define APINFRA_IO_NOC_AO_INFRA_BUS_DCM_REG0_OFF 0 +#define APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_MASK BIT(4) +#define APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_ON BIT(4) +#define APINFRA_MEM_INTF_NOC_AO_INFRA_BUS_DCM_REG0_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_MASK 0x1C +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_MASK 0x90 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_MASK BIT(21) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_MASK BIT(22) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_MASK BIT(20) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_MASK BIT(24) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_MASK BIT(23) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_ON 0x1C +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_ON 0x90 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_ON BIT(21) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_ON BIT(22) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_ON BIT(20) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_ON BIT(24) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_ON BIT(23) +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG0_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG1_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG2_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG3_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG4_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG5_OFF 0 +#define APINFRA_MEM_CTRL_AO_INFRA_BUS_DCM_REG6_OFF 0 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG0_MASK 0x14920 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG1_MASK BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG2_MASK BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG3_MASK BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG0_ON 0x14920 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG1_ON BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG2_ON BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG3_ON BIT(13) +#define PERI_AO_BCRM_PERI_BUS_DCM_REG0_OFF 0 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG1_OFF 0 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG2_OFF 0 +#define PERI_AO_BCRM_PERI_BUS_DCM_REG3_OFF 0 +#define VLP_AO_BCRM_VLP_BUS_DCM_REG0_MASK 0x7C026 +#define VLP_AO_BCRM_VLP_BUS_DCM_REG0_ON 0x26 +#define VLP_AO_BCRM_VLP_BUS_DCM_REG0_OFF 0x6 +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_MASK (0xFFFF0003) +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_ON (0x8A080003) +#define MCUSYS_PAR_WRAP_MCU_BKR_LDCM2_REG0_OFF (0xA0880000) + +void dcm_mcusys_par_wrap_mcu_l3c_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_l3c_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_acp_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_acp_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_adb_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_adb_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_stalldcm(bool on); +bool dcm_mcusys_par_wrap_mcu_stalldcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_apb_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_apb_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_io_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_io_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_bus_qdcm(bool on); +bool dcm_mcusys_par_wrap_mcu_bus_qdcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_core_qdcm(bool on); +bool dcm_mcusys_par_wrap_mcu_core_qdcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_bkr_ldcm1(bool on); +bool dcm_mcusys_par_wrap_mcu_bkr_ldcm1_is_on(void); +void dcm_mcusys_par_wrap_mcu_bkr_ldcm2(bool on); +bool dcm_mcusys_par_wrap_mcu_bkr_ldcm2_is_on(void); +void dcm_mcusys_par_wrap_mcu_cbip_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_cbip_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_misc_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_misc_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_dsu_acp_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_dsu_acp_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_chi_mon_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_chi_mon_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_gic_spi_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_gic_spi_dcm_is_on(void); +void dcm_mcusys_par_wrap_mcu_ebg_dcm(bool on); +bool dcm_mcusys_par_wrap_mcu_ebg_dcm_is_on(void); +void dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm(bool on); +bool dcm_bcrm_apinfra_io_ctrl_ao_infra_bus_dcm_is_on(void); +void dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm(bool on); +bool dcm_bcrm_apinfra_io_noc_ao_infra_bus_dcm_is_on(void); +void dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm(bool on); +bool dcm_bcrm_apinfra_mem_intf_noc_ao_infra_bus_dcm_is_on(void); +void dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm(bool on); +bool dcm_bcrm_apinfra_mem_ctrl_ao_infra_bus_dcm_is_on(void); +void dcm_peri_ao_bcrm_peri_bus1_dcm(bool on); +bool dcm_peri_ao_bcrm_peri_bus1_dcm_is_on(void); +void dcm_peri_ao_bcrm_peri_bus2_dcm(bool on); +bool dcm_peri_ao_bcrm_peri_bus2_dcm_is_on(void); +void dcm_vlp_ao_bcrm_vlp_bus_dcm(bool on); +bool dcm_vlp_ao_bcrm_vlp_bus_dcm_is_on(void); + +#endif /* DCM_MTK_DCM_UTILS_H_ */ diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk index 8ae8e285d..a43050b08 100644 --- a/plat/mediatek/mt8196/platform.mk +++ b/plat/mediatek/mt8196/platform.mk @@ -18,6 +18,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common \ -I${MTK_PLAT}/include \ -I${MTK_PLAT}/include/${ARCH_VERSION} \ -I${MTK_PLAT} \ + -I${MTK_PLAT_SOC}/drivers/dcm/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/include \ -Idrivers/arm/gic \ @@ -57,6 +58,8 @@ BL31_SOURCES += drivers/delay_timer/delay_timer.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/params_setup.c \ ${MTK_PLAT}/drivers/gpio/mtgpio_common.c \ + $(MTK_PLAT)/$(MTK_SOC)/drivers/dcm/mtk_dcm.c \ + $(MTK_PLAT)/$(MTK_SOC)/drivers/dcm/mtk_dcm_utils.c \ $(MTK_PLAT)/$(MTK_SOC)/drivers/gpio/mtgpio.c \ $(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c From 1f913a6e3a3eb6349db9a2263e15594c4dcd5766 Mon Sep 17 00:00:00 2001 From: Guangjie Song Date: Wed, 18 Dec 2024 21:54:45 +0800 Subject: [PATCH 2/2] feat(mt8196): add mtcmos driver add mtcmos driver for ufs power control Signed-off-by: Guangjie Song Change-Id: I3f63d5976906aaca91a71a147497e9345339774d --- plat/mediatek/build_helpers/options.mk | 1 + plat/mediatek/drivers/mtcmos/mt8196/mtcmos.c | 185 +++++++++++++++++++ plat/mediatek/drivers/mtcmos/mt8196/mtcmos.h | 18 ++ plat/mediatek/drivers/mtcmos/rules.mk | 13 ++ plat/mediatek/mt8196/plat_config.mk | 1 + plat/mediatek/mt8196/platform.mk | 2 + 6 files changed, 220 insertions(+) create mode 100644 plat/mediatek/drivers/mtcmos/mt8196/mtcmos.c create mode 100644 plat/mediatek/drivers/mtcmos/mt8196/mtcmos.h create mode 100644 plat/mediatek/drivers/mtcmos/rules.mk diff --git a/plat/mediatek/build_helpers/options.mk b/plat/mediatek/build_helpers/options.mk index 128b14f6d..75cc80aef 100644 --- a/plat/mediatek/build_helpers/options.mk +++ b/plat/mediatek/build_helpers/options.mk @@ -24,3 +24,4 @@ $(eval $(call add_defined_option,CONFIG_MTK_CPU_SUSPEND_EN)) $(eval $(call add_defined_option,CONFIG_MTK_PM_ARCH)) $(eval $(call add_defined_option,CONFIG_MTK_CPU_PM_ARCH)) $(eval $(call add_defined_option,CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND)) +$(eval $(call add_defined_option,CONFIG_MTK_MTCMOS)) diff --git a/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.c b/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.c new file mode 100644 index 000000000..ee3849fdf --- /dev/null +++ b/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2025, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include + +#include +#include +#include +#include +#include + +#include + +#define SPM_PROJECT_CODE 0xB16 + +#define PWR_RST_B BIT(0) +#define PWR_ISO BIT(1) +#define PWR_ON BIT(2) +#define PWR_ON_2ND BIT(3) +#define PWR_CLK_DIS BIT(4) +#define RTFF_SAVE BIT(24) +#define RTFF_NRESTORE BIT(25) +#define RTFF_CLK_DIS BIT(26) +#define RTFF_SAVE_FLAG BIT(27) +#define PWR_ACK BIT(30) +#define PWR_ACK_2ND BIT(31) + +#define UFS0_SRAM_PDN BIT(8) +#define UFS0_SRAM_PDN_ACK BIT(12) + +#define POWERON_CONFIG_EN (SPM_BASE + 0x0) +#define UFS0_PWR_CON (SPM_BASE + 0xE2C) +#define UFS0_PHY_PWR_CON (SPM_BASE + 0xE30) + +#define SPM_BUS_PROTECT_EN_SET (SPM_BASE + 0x90DC) +#define SPM_BUS_PROTECT_EN_CLR (SPM_BASE + 0x90E0) +#define SPM_BUS_PROTECT_CG_EN_SET (SPM_BASE + 0x90F4) +#define SPM_BUS_PROTECT_CG_EN_CLR (SPM_BASE + 0x90F8) +#define SPM_BUS_PROTECT_RDY_STA (SPM_BASE + 0x9208) + +#define UFS0_PROT_STEP1_MASK BIT(11) +#define UFS0_PHY_PROT_STEP1_MASK BIT(12) + +enum { + RELEASE_BUS_PROTECT, + SET_BUS_PROTECT +}; + +#define MTCMOS_TIMEOUT_US 500 + +#define ETIMEDOUT 25 + +static spinlock_t mtcmos_ctrl_lock; + +static int mtcmos_wait_for_state(uint32_t reg, uint32_t mask, bool is_set) +{ + uint32_t retry = MTCMOS_TIMEOUT_US; + uint32_t expect = is_set ? mask : 0; + + do { + if ((mmio_read_32(reg) & mask) == expect) + return 0; + udelay(1); + retry--; + } while (retry); + + ERROR("%s(0x%x, 0x%x, %d) timeout, reg_val=0x%x\n", + __func__, reg, mask, is_set, mmio_read_32(reg)); + + return -ETIMEDOUT; +} + + +static int spm_mtcmos_ctrl_bus_prot(int state, uint32_t mask) +{ + mmio_write_32(SPM_BUS_PROTECT_CG_EN_SET, mask); + + if (state == SET_BUS_PROTECT) { + mmio_write_32(SPM_BUS_PROTECT_EN_SET, mask); + if (mtcmos_wait_for_state(SPM_BUS_PROTECT_RDY_STA, mask, + true)) + return -ETIMEDOUT; + } else if (state == RELEASE_BUS_PROTECT) { + mmio_write_32(SPM_BUS_PROTECT_EN_CLR, mask); + } + + mmio_write_32(SPM_BUS_PROTECT_CG_EN_CLR, mask); + + return 0; +} + +int spm_mtcmos_ctrl(enum mtcmos_state state, uintptr_t reg, uint32_t mask) +{ + int ret = 0; + + spin_lock(&mtcmos_ctrl_lock); + + mmio_write_32(POWERON_CONFIG_EN, (SPM_PROJECT_CODE << 16) | BIT(0)); + + if (state == STA_POWER_DOWN) { + ret = spm_mtcmos_ctrl_bus_prot(SET_BUS_PROTECT, mask); + if (ret) + goto exit; + + if (reg == UFS0_PWR_CON) { + mmio_setbits_32(reg, UFS0_SRAM_PDN); + ret = mtcmos_wait_for_state(reg, UFS0_SRAM_PDN_ACK, + true); + if (ret) + goto exit; + } + + mmio_setbits_32(reg, RTFF_CLK_DIS); + mmio_setbits_32(reg, RTFF_SAVE); + mmio_clrbits_32(reg, RTFF_SAVE); + mmio_clrbits_32(reg, RTFF_CLK_DIS); + mmio_setbits_32(reg, RTFF_SAVE_FLAG); + + mmio_setbits_32(reg, PWR_ISO); + mmio_setbits_32(reg, PWR_CLK_DIS); + mmio_clrbits_32(reg, PWR_RST_B); + + mmio_clrbits_32(reg, PWR_ON); + ret = mtcmos_wait_for_state(reg, PWR_ACK, false); + if (ret) + goto exit; + + mmio_clrbits_32(reg, PWR_ON_2ND); + ret = mtcmos_wait_for_state(reg, PWR_ACK_2ND, false); + if (ret) + goto exit; + } else if (state == STA_POWER_ON) { + mmio_setbits_32(reg, PWR_ON); + ret = mtcmos_wait_for_state(reg, PWR_ACK, true); + if (ret) + goto exit; + + udelay(50); + + mmio_setbits_32(reg, PWR_ON_2ND); + ret = mtcmos_wait_for_state(reg, PWR_ACK_2ND, true); + if (ret) + goto exit; + + mmio_clrbits_32(reg, PWR_CLK_DIS); + mmio_clrbits_32(reg, PWR_ISO); + udelay(10); + mmio_setbits_32(reg, PWR_RST_B); + + if ((mmio_read_32(reg) & RTFF_SAVE_FLAG) == RTFF_SAVE_FLAG) { + mmio_setbits_32(reg, RTFF_CLK_DIS); + mmio_clrbits_32(reg, RTFF_NRESTORE); + mmio_setbits_32(reg, RTFF_NRESTORE); + mmio_clrbits_32(reg, RTFF_CLK_DIS); + } + + if (reg == UFS0_PWR_CON) { + mmio_clrbits_32(UFS0_PWR_CON, UFS0_SRAM_PDN); + ret = mtcmos_wait_for_state(UFS0_PWR_CON, + UFS0_SRAM_PDN_ACK, + false); + if (ret) + goto exit; + } + + spm_mtcmos_ctrl_bus_prot(RELEASE_BUS_PROTECT, mask); + } + +exit: + spin_unlock(&mtcmos_ctrl_lock); + return ret; +} + +int spm_mtcmos_ctrl_ufs0(enum mtcmos_state state) +{ + return spm_mtcmos_ctrl(state, UFS0_PWR_CON, UFS0_PROT_STEP1_MASK); +} + +int spm_mtcmos_ctrl_ufs0_phy(enum mtcmos_state state) +{ + return spm_mtcmos_ctrl(state, UFS0_PHY_PWR_CON, + UFS0_PHY_PROT_STEP1_MASK); +} diff --git a/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.h b/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.h new file mode 100644 index 000000000..39902bcfc --- /dev/null +++ b/plat/mediatek/drivers/mtcmos/mt8196/mtcmos.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ +#define PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ + +enum mtcmos_state { + STA_POWER_DOWN, + STA_POWER_ON, +}; + +int spm_mtcmos_ctrl_ufs0(enum mtcmos_state state); +int spm_mtcmos_ctrl_ufs0_phy(enum mtcmos_state state); + +#endif /* PLAT_MEDIATEK_DRIVERS_MTCMOS_MT8196_MTCMOS_H_ */ diff --git a/plat/mediatek/drivers/mtcmos/rules.mk b/plat/mediatek/drivers/mtcmos/rules.mk new file mode 100644 index 000000000..a8f1df2f6 --- /dev/null +++ b/plat/mediatek/drivers/mtcmos/rules.mk @@ -0,0 +1,13 @@ +# +# Copyright (c) 2025, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := mtcmos +LOCAL_SRCS-y := $(LOCAL_DIR)/${MTK_SOC}/mtcmos.c + +PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk index 0239a3f65..c6531525f 100644 --- a/plat/mediatek/mt8196/plat_config.mk +++ b/plat/mediatek/mt8196/plat_config.mk @@ -42,6 +42,7 @@ CONFIG_MTK_CPU_PM_SUPPORT := y CONFIG_MTK_CPU_PM_ARCH := 5_4 CONFIG_MTK_SMP_EN := n CONFIG_MTK_CPU_SUSPEND_EN := y +CONFIG_MTK_MTCMOS := y CONFIG_MTK_SPM_VERSION := mt8196 CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND := y CONFIG_MTK_TINYSYS_VCP := y diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk index a43050b08..d13b65aa0 100644 --- a/plat/mediatek/mt8196/platform.mk +++ b/plat/mediatek/mt8196/platform.mk @@ -35,6 +35,8 @@ MODULES-y += $(MTK_PLAT)/drivers/vcp MODULES-y += $(MTK_PLAT)/helpers MODULES-y += $(MTK_PLAT)/topology +MODULES-$(CONFIG_MTK_MTCMOS) += $(MTK_PLAT)/drivers/mtcmos + ifneq ($(MTKLIB_PATH),) LDFLAGS += -L $(dir $(MTKLIB_PATH)) LDLIBS += -l$(patsubst lib%.a,%,$(notdir $(MTKLIB_PATH)))