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drivers/marvell/mochi: add support for cn913x in PCIe EP mode

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Change-Id: I4dc33d1eb59395605f64e5aad5cafa10c53265cc
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20453
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
This commit is contained in:
Konstantin Porotchkin 2019-12-17 16:09:00 +02:00
parent c82cf21d6e
commit 2bcde264f3
1 changed files with 3 additions and 2 deletions
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5
drivers/marvell/mochi/cp110_setup.c
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@ -186,8 +186,9 @@ static void cp110_pcie_clk_cfg(uintptr_t base)
pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET;
pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET;
/* CP110 revision A2 */
if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2) {
/* CP110 revision A2 or CN913x */
if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2 ||
cp110_device_id_get(base) == MVEBU_CN9130_DEV_ID) {
/*
* PCIe Reference Clock Buffer Control register must be
* set according to the clock direction (input/output)