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doc: renesas: Document platforms based on RZ/G2 SoC's
Document the platforms based on RZ/G2 SoC's. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I9ce5b9df3573b1198c5c7be79b5471d54573609a
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Biju Das
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@ -486,6 +486,17 @@ Renesas rcar-gen3 platform port
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:F: drivers/renesas/rcar
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:F: drivers/renesas/rcar
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:F: tools/renesas/rcar_layout_create
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:F: tools/renesas/rcar_layout_create
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Renesas RZ/G2 platform port
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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:M: Biju Das <biju.das.jz@bp.renesas.com>
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:G: `bijucdas`_
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:F: docs/plat/rz-g2.rst
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:F: plat/renesas/common
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:F: plat/renesas/rzg
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:F: drivers/renesas/common
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:F: drivers/renesas/rzg
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:F: tools/renesas/rzg_layout_create
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RockChip platform port
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RockChip platform port
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^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^
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:M: Tony Xie <tony.xie@rock-chips.com>
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:M: Tony Xie <tony.xie@rock-chips.com>
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@ -601,6 +612,7 @@ Build system
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.. _AlexeiFedorov: https://github.com/AlexeiFedorov
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.. _AlexeiFedorov: https://github.com/AlexeiFedorov
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.. _Andre-ARM: https://github.com/Andre-ARM
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.. _Andre-ARM: https://github.com/Andre-ARM
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.. _Anson-Huang: https://github.com/Anson-Huang
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.. _Anson-Huang: https://github.com/Anson-Huang
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.. _bijucdas: https://github.com/bijucdas
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.. _bryanodonoghue: https://github.com/bryanodonoghue
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.. _bryanodonoghue: https://github.com/bryanodonoghue
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.. _b49020: https://github.com/b49020
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.. _b49020: https://github.com/b49020
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.. _carlocaione: https://github.com/carlocaione
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.. _carlocaione: https://github.com/carlocaione
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@ -32,6 +32,7 @@ Platform Ports
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rpi3
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rpi3
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rpi4
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rpi4
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rcar-gen3
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rcar-gen3
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rz-g2
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rockchip
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rockchip
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socionext-uniphier
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socionext-uniphier
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synquacer
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synquacer
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228
docs/plat/rz-g2.rst
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228
docs/plat/rz-g2.rst
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@ -0,0 +1,228 @@
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Renesas RZ/G
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============
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The "RZ/G" Family of high-end 64-bit Arm®-based microprocessors (MPUs)
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enables the solutions required for the smart society of the future.
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Through a variety of Arm Cortex®-A53 and A57-based devices, engineers can
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easily implement high-resolution human machine interfaces (HMI), embedded
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vision, embedded artificial intelligence (e-AI) and real-time control and
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industrial ethernet connectivity.
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The scalable RZ/G hardware platform and flexible software platform
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cover the full product range, from the premium class to the entry
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level. Plug-ins are available for multiple open-source software tools.
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Renesas RZ/G2 reference platforms:
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----------------------------------
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+--------------+----------------------------------------------------------------------------------+
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| Board | Details |
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+==============+===============+==================================================================+
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| hihope-rzg2h | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2H SoC |
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| +----------------------------------------------------------------------------------+
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| | http://hihope.org/product/musashi |
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+--------------+----------------------------------------------------------------------------------+
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| hihope-rzg2m | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2M SoC |
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| +----------------------------------------------------------------------------------+
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| | http://hihope.org/product/musashi |
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+--------------+----------------------------------------------------------------------------------+
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| hihope-rzg2n | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2N SoC |
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| +----------------------------------------------------------------------------------+
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| | http://hihope.org/product/musashi |
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+--------------+----------------------------------------------------------------------------------+
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| ek874 | "96 boards" compatible board from Silicon Linux equipped with Renesas RZ/G2E SoC |
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| +----------------------------------------------------------------------------------+
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| | https://www.si-linux.co.jp/index.php?CAT%2FCAT874 |
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+--------------+----------------------------------------------------------------------------------+
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`boards info <https://www.renesas.com/us/en/products/rzg-linux-platform/rzg-marcketplace/board-solutions.html#rzg2>`__
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The current TF-A port has been tested on the HiHope RZ/G2M
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SoC_id r8a774a1 revision ES1.3.
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::
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ARM CA57 (ARMv8) 1.5 GHz dual core, with NEON/VFPv4, L1$ I/D 48K/32K, L2$ 1MB
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ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K, L2$ 512K
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Memory controller for LPDDR4-3200 4GB in 2 channels(32-bit bus mode)
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Two- and three-dimensional graphics engines,
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Video processing units,
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Display Output,
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Video Input,
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SD card host interface,
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USB3.0 and USB2.0 interfaces,
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CAN interfaces,
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Ethernet AVB,
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Wi-Fi + BT,
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PCI Express Interfaces,
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Memories
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INTERNAL 384KB SYSTEM RAM
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DDR 4 GB LPDDR4
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QSPI FLASH 64MB
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EMMC 32 GB EMMC (HS400 240 MBYTES/S)
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MICROSD-CARD SLOT (SDR104 100 MBYTES/S)
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Overview
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--------
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On RZ/G2 SoCs the BOOTROM starts the cpu at EL3; for this port BL2
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will therefore be entered at this exception level (the Renesas' ATF
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reference tree [1] resets into EL1 before entering BL2 - see its
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bl2.ld.S)
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BL2 initializes DDR before determining the boot reason (cold or warm).
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Once BL2 boots, it determines the boot reason, writes it to shared
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memory (BOOT_KIND_BASE) together with the BL31 parameters
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(PARAMS_BASE) and jumps to BL31.
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To all effects, BL31 is as if it is being entered in reset mode since
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it still needs to initialize the rest of the cores; this is the reason
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behind using direct shared memory access to BOOT_KIND_BASE _and_
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PARAMS_BASE instead of using registers to get to those locations (see
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el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
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case).
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[1] https://github.com/renesas-rz/meta-rzg2/tree/BSP-1.0.5/recipes-bsp/arm-trusted-firmware/files
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How to build
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------------
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The TF-A build options depend on the target board so you will have to
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refer to those specific instructions. What follows is customized to
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the HiHope RZ/G2M development kit used in this port.
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Build Tested:
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~~~~~~~~~~~~~
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.. code:: bash
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make bl2 bl31 rzg LOG_LEVEL=40 PLAT=rzg LSI=G2M RCAR_DRAM_SPLIT=2\
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RCAR_LOSSY_ENABLE=1 SPD="none" MBEDTLS_DIR=$mbedtls
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System Tested:
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~~~~~~~~~~~~~~
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* mbed_tls:
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git@github.com:ARMmbed/mbedtls.git [devel]
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| commit 72ca39737f974db44723760623d1b29980c00a88
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| Merge: ef94c4fcf dd9ec1c57
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| Author: Janos Follath <janos.follath@arm.com>
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| Date: Wed Oct 7 09:21:01 2020 +0100
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* u-boot:
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The port has beent tested using mainline uboot with HiHope RZ/G2M board
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specific patches.
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| commit 46ce9e777c1314ccb78906992b94001194eaa87b
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| Author: Heiko Schocher <hs@denx.de>
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| Date: Tue Nov 3 15:22:36 2020 +0100
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* linux:
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The port has beent tested using mainline kernel.
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| commit f8394f232b1eab649ce2df5c5f15b0e528c92091
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| Author: Linus Torvalds <torvalds@linux-foundation.org>
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| Date: Sun Nov 8 16:10:16 2020 -0800
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| Linux 5.10-rc3
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TF-A Build Procedure
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~~~~~~~~~~~~~~~~~~~~
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- Fetch all the above 3 repositories.
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- Prepare the AARCH64 toolchain.
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- Build u-boot using hihope_rzg2_defconfig.
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Result: u-boot-elf.srec
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.. code:: bash
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make CROSS_COMPILE=aarch64-linux-gnu-
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hihope_rzg2_defconfig
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make CROSS_COMPILE=aarch64-linux-gnu-
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- Build TF-A
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Result: bootparam_sa0.srec, cert_header_sa6.srec, bl2.srec, bl31.srec
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.. code:: bash
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make bl2 bl31 rzg LOG_LEVEL=40 PLAT=rzg LSI=G2M RCAR_DRAM_SPLIT=2\
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RCAR_LOSSY_ENABLE=1 SPD="none" MBEDTLS_DIR=$mbedtls
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Install Procedure
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~~~~~~~~~~~~~~~~~
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- Boot the board in Mini-monitor mode and enable access to the
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QSPI flash.
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- Use the flash_writer utility[2] to flash all the SREC files.
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[2] https://github.com/renesas-rz/rzg2_flash_writer
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Boot trace
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----------
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::
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INFO: ARM GICv2 driver initialized
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NOTICE: BL2: RZ/G2 Initial Program Loader(CA57) Rev.2.0.6
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NOTICE: BL2: PRR is RZ/G2M Ver.1.3
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NOTICE: BL2: Board is HiHope RZ/G2M Rev.4.0
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NOTICE: BL2: Boot device is QSPI Flash(40MHz)
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NOTICE: BL2: LCM state is unknown
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NOTICE: BL2: DDR3200(rev.0.40)
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NOTICE: BL2: [COLD_BOOT]
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NOTICE: BL2: DRAM Split is 2ch
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NOTICE: BL2: QoS is default setting(rev.0.19)
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NOTICE: BL2: DRAM refresh interval 1.95 usec
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NOTICE: BL2: Periodic Write DQ Training
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NOTICE: BL2: CH0: 400000000 - 47fffffff, 2 GiB
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NOTICE: BL2: CH2: 600000000 - 67fffffff, 2 GiB
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NOTICE: BL2: Lossy Decomp areas
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NOTICE: Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570
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NOTICE: Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0
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NOTICE: Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0
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NOTICE: BL2: FDT at 0xe631db30
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NOTICE: BL2: v2.3(release):v2.4-rc0-2-g1433701e5
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NOTICE: BL2: Built : 13:45:26, Nov 7 2020
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NOTICE: BL2: Normal boot
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INFO: BL2: Doing platform setup
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INFO: BL2: Loading image id 3
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NOTICE: BL2: dst=0xe631d200 src=0x8180000 len=512(0x200)
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NOTICE: BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800)
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WARNING: r-car ignoring the BL31 size from certificate,using RCAR_TRUSTED_SRAM_SIZE instead
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INFO: Loading image id=3 at address 0x44000000
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NOTICE: rcar_file_len: len: 0x0003e000
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NOTICE: BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000)
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INFO: Image id=3 loaded: 0x44000000 - 0x4403e000
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INFO: BL2: Loading image id 5
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INFO: Loading image id=5 at address 0x50000000
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NOTICE: rcar_file_len: len: 0x00100000
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NOTICE: BL2: dst=0x50000000 src=0x8300000 len=1048576(0x100000)
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INFO: Image id=5 loaded: 0x50000000 - 0x50100000
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NOTICE: BL2: Booting BL31
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INFO: Entry point address = 0x44000000
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INFO: SPSR = 0x3cd
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U-Boot 2021.01-rc1-00244-gac37e14fbd (Nov 04 2020 - 20:03:34 +0000)
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CPU: Renesas Electronics R8A774A1 rev 1.3
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Model: HopeRun HiHope RZ/G2M with sub board
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DRAM: 3.9 GiB
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MMC: mmc@ee100000: 0, mmc@ee160000: 1
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Loading Environment from MMC... OK
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In: serial@e6e88000
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Out: serial@e6e88000
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Err: serial@e6e88000
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Net: eth0: ethernet@e6800000
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Hit any key to stop autoboot: 0
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=>
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