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feat(imx8m): move the gpc reg & macro to a separate header file

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move the gpc reg offset, bit define & macro to a separate header
file for code reuse.

This fixes suspend to mem on i.MX8M Plus too, since the register
layout is different there.

Change-Id: Ibec60c3a68ffa8c378de5334577a7b0e463ca875
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Upgrade to latest, update commit message
This commit is contained in:
Jacky Bai 2020-03-23 15:54:01 +08:00 • committed by Marek Vasut
parent 5f01b0b116
commit 2a6ffa99af
2 changed files with 9 additions and 59 deletions
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27
plat/imx/imx8m/ddr/dram_retention.c
View file

@ -8,14 +8,12 @@
#include <lib/mmio.h> #include <lib/mmio.h>
#include <dram.h> #include <dram.h>
#include <gpc_reg.h>
#include <platform_def.h> #include <platform_def.h>
#define SRC_DDR1_RCR (IMX_SRC_BASE + 0x1000) #define SRC_DDR1_RCR (IMX_SRC_BASE + 0x1000)
#define SRC_DDR2_RCR (IMX_SRC_BASE + 0x1004) #define SRC_DDR2_RCR (IMX_SRC_BASE + 0x1004)
#define PU_PGC_UP_TRG 0xf8
#define PU_PGC_DN_TRG 0x104
#define GPC_PU_PWRHSK (IMX_GPC_BASE + 0x01FC)
#define CCM_SRC_CTRL_OFFSET (IMX_CCM_BASE + 0x800) #define CCM_SRC_CTRL_OFFSET (IMX_CCM_BASE + 0x800)
#define CCM_CCGR_OFFSET (IMX_CCM_BASE + 0x4000) #define CCM_CCGR_OFFSET (IMX_CCM_BASE + 0x4000)
#define CCM_TARGET_ROOT_OFFSET (IMX_CCM_BASE + 0x8000) #define CCM_TARGET_ROOT_OFFSET (IMX_CCM_BASE + 0x8000)
@ -102,21 +100,12 @@ void dram_enter_retention(void)
} }
dwc_ddrphy_apb_wr(0xd0000, 0x1); dwc_ddrphy_apb_wr(0xd0000, 0x1);
#if defined(PLAT_imx8mq)
/* pwrdnreqn_async adbm/adbs of ddr */ /* pwrdnreqn_async adbm/adbs of ddr */
mmio_clrbits_32(GPC_PU_PWRHSK, BIT(1)); mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, DDRMIX_ADB400_SYNC);
while (mmio_read_32(GPC_PU_PWRHSK) & BIT(18)) { while (mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & DDRMIX_ADB400_ACK)
; ;
} mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, DDRMIX_ADB400_SYNC);
mmio_setbits_32(GPC_PU_PWRHSK, BIT(1));
#else
/* pwrdnreqn_async adbm/adbs of ddr */
mmio_clrbits_32(GPC_PU_PWRHSK, BIT(2));
while (mmio_read_32(GPC_PU_PWRHSK) & BIT(20)) {
;
}
mmio_setbits_32(GPC_PU_PWRHSK, BIT(2));
#endif
/* remove PowerOk */ /* remove PowerOk */
mmio_write_32(SRC_DDR1_RCR, 0x8F000008); mmio_write_32(SRC_DDR1_RCR, 0x8F000008);
@ -124,8 +113,8 @@ void dram_enter_retention(void)
mmio_write_32(CCM_SRC_CTRL(15), 2); mmio_write_32(CCM_SRC_CTRL(15), 2);
/* enable the phy iso */ /* enable the phy iso */
mmio_setbits_32(IMX_GPC_BASE + 0xd40, 1); mmio_setbits_32(IMX_GPC_BASE + DDRMIX_PGC, 1);
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, BIT(5)); mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, DDRMIX_PWR_REQ);
VERBOSE("dram enter retention\n"); VERBOSE("dram enter retention\n");
} }
@ -150,7 +139,7 @@ void dram_exit_retention(void)
mmio_write_32(CCM_TARGET_ROOT(65) + 0x4, (0x4 << 24) | (0x3 << 16)); mmio_write_32(CCM_TARGET_ROOT(65) + 0x4, (0x4 << 24) | (0x3 << 16));
/* disable iso */ /* disable iso */
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, BIT(5)); mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, DDRMIX_PWR_REQ);
mmio_write_32(SRC_DDR1_RCR, 0x8F000006); mmio_write_32(SRC_DDR1_RCR, 0x8F000006);
/* wait dram pll locked */ /* wait dram pll locked */

41
plat/imx/imx8m/imx8mm/gpc.c
View file

@ -19,46 +19,7 @@
#include <gpc.h> #include <gpc.h>
#include <imx_sip_svc.h> #include <imx_sip_svc.h>
#define MIPI_PWR_REQ BIT(0) #define CCGR(x) (0x4000 + (x) * 16)
#define PCIE_PWR_REQ BIT(1)
#define OTG1_PWR_REQ BIT(2)
#define OTG2_PWR_REQ BIT(3)
#define HSIOMIX_PWR_REQ BIT(4)
#define GPU2D_PWR_REQ BIT(6)
#define GPUMIX_PWR_REQ BIT(7)
#define VPUMIX_PWR_REQ BIT(8)
#define GPU3D_PWR_REQ BIT(9)
#define DISPMIX_PWR_REQ BIT(10)
#define VPU_G1_PWR_REQ BIT(11)
#define VPU_G2_PWR_REQ BIT(12)
#define VPU_H1_PWR_REQ BIT(13)
#define HSIOMIX_ADB400_SYNC (0x3 << 5)
#define DISPMIX_ADB400_SYNC BIT(7)
#define VPUMIX_ADB400_SYNC BIT(8)
#define GPU3D_ADB400_SYNC BIT(9)
#define GPU2D_ADB400_SYNC BIT(10)
#define GPUMIX_ADB400_SYNC BIT(11)
#define HSIOMIX_ADB400_ACK (0x3 << 23)
#define DISPMIX_ADB400_ACK BIT(25)
#define VPUMIX_ADB400_ACK BIT(26)
#define GPU3D_ADB400_ACK BIT(27)
#define GPU2D_ADB400_ACK BIT(28)
#define GPUMIX_ADB400_ACK BIT(29)
#define MIPI_PGC 0xc00
#define PCIE_PGC 0xc40
#define OTG1_PGC 0xc80
#define OTG2_PGC 0xcc0
#define HSIOMIX_PGC 0xd00
#define GPU2D_PGC 0xd80
#define GPUMIX_PGC 0xdc0
#define VPUMIX_PGC 0xe00
#define GPU3D_PGC 0xe40
#define DISPMIX_PGC 0xe80
#define VPU_G1_PGC 0xec0
#define VPU_G2_PGC 0xf00
#define VPU_H1_PGC 0xf40
enum pu_domain_id { enum pu_domain_id {
HSIOMIX, HSIOMIX,