From 29f8a952cbbc7ee91188464cdf01b243735d41f8 Mon Sep 17 00:00:00 2001
From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Date: Mon, 20 Jan 2025 16:02:21 +0200
Subject: [PATCH] feat(nxp-clk): add base address for PERIPH_DFS
The PERIPH_DFS module is used to clock the SD and QSPI modules.
Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
---
drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h | 1 +
drivers/nxp/clk/s32cc/s32cc_clk_drv.c | 8 +++++++-
include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h | 1 +
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
index 665930b2e..46ef999df 100644
--- a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
+++ b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
@@ -11,6 +11,7 @@
#define ARMPLL_BASE_ADDR (0x40038000UL)
#define PERIPHPLL_BASE_ADDR (0x4003C000UL)
#define ARM_DFS_BASE_ADDR (0x40054000UL)
+#define PERIPH_DFS_BASE_ADDR (0x40058000UL)
#define CGM0_BASE_ADDR (0x40030000UL)
#define CGM1_BASE_ADDR (0x40034000UL)
#define DDRPLL_BASE_ADDR (0x40044000UL)
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index c235e046f..fa56a141b 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -24,6 +24,7 @@ struct s32cc_clk_drv {
uintptr_t armpll_base;
uintptr_t periphpll_base;
uintptr_t armdfs_base;
+ uintptr_t periphdfs_base;
uintptr_t cgm0_base;
uintptr_t cgm1_base;
uintptr_t cgm5_base;
@@ -58,6 +59,7 @@ static struct s32cc_clk_drv *get_drv(void)
.armpll_base = ARMPLL_BASE_ADDR,
.periphpll_base = PERIPHPLL_BASE_ADDR,
.armdfs_base = ARM_DFS_BASE_ADDR,
+ .periphdfs_base = PERIPH_DFS_BASE_ADDR,
.cgm0_base = CGM0_BASE_ADDR,
.cgm1_base = CGM1_BASE_ADDR,
.cgm5_base = MC_CGM5_BASE_ADDR,
@@ -110,6 +112,9 @@ static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *d
case S32CC_ARM_DFS:
*base = drv->armdfs_base;
break;
+ case S32CC_PERIPH_DFS:
+ *base = drv->periphdfs_base;
+ break;
case S32CC_CGM0:
*base = drv->cgm0_base;
break;
@@ -1980,11 +1985,12 @@ static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id)
static int s32cc_clk_mmap_regs(const struct s32cc_clk_drv *drv)
{
- const uintptr_t base_addrs[11] = {
+ const uintptr_t base_addrs[12] = {
drv->fxosc_base,
drv->armpll_base,
drv->periphpll_base,
drv->armdfs_base,
+ drv->periphdfs_base,
drv->cgm0_base,
drv->cgm1_base,
drv->cgm5_base,
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
index c91f3b647..50e7a0c0c 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
@@ -37,6 +37,7 @@ enum s32cc_clk_source {
S32CC_CGM0,
S32CC_CGM1,
S32CC_DDR_PLL,
+ S32CC_PERIPH_DFS,
S32CC_CGM5,
};