Merge changes from topic "jc/tc_fw_handoff" into integration

* changes:
  feat(tc): port BL31-BL33 interface to firmware handoff framework
  feat(tc): port BL2-BL31 interface to firmware handoff framework
  feat(tc): port BL1-BL2 interface to firmware handoff framework

include/drivers/arm/css/css_scp.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -45,8 +45,11 @@ int css_scp_boot_ready(void);
 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
 
+#if !TRANSFER_LIST
 CASSERT(SCP_BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
 CASSERT(SCP_BL2U_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
+#endif /* !TRANSFER_LIST */
+
 #endif
 
 #endif /* CSS_SCP_H */

plat/arm/board/tc/include/platform_def.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -34,6 +34,28 @@
 
 #define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00080000	/* 512 KB */
 
+#if TRANSFER_LIST
+/*
+ * Summation of data size of all Transfer Entries included in the Transfer list.
+ * Note: Update this field whenever new Transfer Entries are added in future.
+ */
+#define PLAT_ARM_FW_HANDOFF_SIZE	U(0x9000)
+#define PLAT_ARM_EL3_FW_HANDOFF_BASE	ARM_BL_RAM_BASE
+#define PLAT_ARM_EL3_FW_HANDOFF_LIMIT	PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE
+#define FW_NS_HANDOFF_BASE		(PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE)
+
+/* Mappings for Secure and Non-secure Transfer_list */
+#define TC_MAP_EL3_FW_HANDOFF		MAP_REGION_FLAT(		\
+					PLAT_ARM_EL3_FW_HANDOFF_BASE,	\
+					PLAT_ARM_FW_HANDOFF_SIZE,	\
+					MT_MEMORY | MT_RW | EL3_PAS)
+
+#define TC_MAP_FW_NS_HANDOFF		MAP_REGION_FLAT(		\
+					FW_NS_HANDOFF_BASE,		\
+					PLAT_ARM_FW_HANDOFF_SIZE,	\
+					MT_MEMORY | MT_RW | MT_NS)
+#endif /* TRANSFER_LIST */
+
 /*
  * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC,
  * its base is ARM_AP_TZC_DRAM1_BASE.

plat/arm/board/tc/tc_bl2_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2021-2025, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,17 +18,26 @@
  ******************************************************************************/
 struct bl_params *plat_get_next_bl_params(void)
 {
-	struct bl_params *arm_bl_params = arm_get_next_bl_params();
-
-	const struct dyn_cfg_dtb_info_t *fw_config_info;
+	struct bl_params *arm_bl_params;
 	bl_mem_params_node_t *param_node;
-	uintptr_t fw_config_base = 0U;
-	entry_point_info_t *ep_info;
+	const struct dyn_cfg_dtb_info_t *fw_config_info __maybe_unused;
+	uintptr_t fw_config_base __maybe_unused;
+	entry_point_info_t *ep_info __maybe_unused;
+
+	arm_bl_params = arm_get_next_bl_params();
 
 	/* Get BL31 image node */
 	param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
 	assert(param_node != NULL);
+#if TRANSFER_LIST
+	assert(arm_bl_params != NULL);
 
+	arm_bl_params->head = &param_node->params_node_mem;
+	arm_bl_params->head->ep_info = &param_node->ep_info;
+	arm_bl_params->head->image_id = param_node->image_id;
+
+	arm_bl2_setup_next_ep_info(param_node);
+#else
 	/* Get fw_config load address */
 	fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
 	assert(fw_config_info != NULL);
@@ -42,6 +51,7 @@ struct bl_params *plat_get_next_bl_params(void)
 	 */
 	ep_info = &param_node->ep_info;
 	ep_info->args.arg1 = (uint32_t)fw_config_base;
+#endif /* TRANSFER_LIST */
 
 	return arm_bl_params;
 }

plat/arm/board/tc/tc_bl31_setup.c

@@ -159,8 +159,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 	arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
 
+#if !TRANSFER_LIST
 	/* Fill the properties struct with the info from the config dtb */
 	fconf_populate("FW_CONFIG", arg1);
+#endif
 }
 
 #ifdef PLATFORM_TESTS
@@ -205,6 +207,13 @@ void __init bl31_plat_arch_setup(void)
 {
 	arm_bl31_plat_arch_setup();
 
+	/*
+	 * When TRANSFER_LIST is enabled, HW_CONFIG is included in Transfer List
+	 * as an entry with the tag TL_TAG_FDT. In this case, the configuration
+	 * is already available, so the fconf_populate mechanism is not needed.
+	 * The code block below is only required when TRANSFER_LIST is not used.
+	 */
+#if !TRANSFER_LIST
 	/* HW_CONFIG was also loaded by BL2 */
 	const struct dyn_cfg_dtb_info_t *hw_config_info;
 
@@ -212,6 +221,7 @@ void __init bl31_plat_arch_setup(void)
 	assert(hw_config_info != NULL);
 
 	fconf_populate("HW_CONFIG", hw_config_info->config_addr);
+#endif
 }
 
 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)

plat/arm/board/tc/tc_plat.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,6 +33,9 @@ const mmap_region_t plat_arm_mmap[] = {
 	TC_MAP_NS_DRAM1,
 	TC_FLASH0_RO,
 	TC_MAP_DEVICE,
+#if TRANSFER_LIST
+	TC_MAP_EL3_FW_HANDOFF,
+#endif
 	{0}
 };
 #endif
@@ -58,6 +61,9 @@ const mmap_region_t plat_arm_mmap[] = {
 #ifdef SPD_opteed
 	ARM_MAP_OPTEE_CORE_MEM,
 	ARM_OPTEE_PAGEABLE_LOAD_MEM,
+#endif
+#if TRANSFER_LIST
+	TC_MAP_EL3_FW_HANDOFF,
 #endif
 	{0}
 };
@@ -71,6 +77,10 @@ const mmap_region_t plat_arm_mmap[] = {
 	PLAT_DTB_DRAM_NS,
 #if SPM_MM
 	ARM_SPM_BUF_EL3_MMAP,
+#endif
+#if TRANSFER_LIST
+	TC_MAP_FW_NS_HANDOFF,
+	TC_MAP_EL3_FW_HANDOFF,
 #endif
 	{0}
 };