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feat(fvp_r): configure system registers to boot rich OS

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Following system registers are modified before exiting EL2 to allow
u-boot/Linux to boot
  1. CNTHCTL_EL2.EL1PCTEN -> 1
     Allows U-boot to use physical counters at EL1
  2. VTCR_EL2.MSA -> 1
     Enables VMSA at EL1, which is required by U-Boot and Linux.
  3. HCR_EL2.APK = 1 & HCR_EL2.API = 1
     Disables PAuth instruction and register traps in EL1

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I58f45b6669a9ad1debb80265b243015c054a9bb1
This commit is contained in:
Manish Pandey 2021-10-06 17:28:09 +01:00
parent 4796c6ca89
commit 28bbbf3bf5
4 changed files with 54 additions and 20 deletions
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4
include/arch/aarch64/arch.h
View file

@ -576,6 +576,10 @@
#define CPTR_EL2_TZ_BIT (U(1) << 8)
#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
/* VTCR_EL2 definitions */
#define VTCR_RESET_VAL U(0x0)
#define VTCR_EL2_MSA (U(1) << 31)
/* CPSR/SPSR definitions */
#define DAIF_FIQ_BIT (U(1) << 0)
#define DAIF_IRQ_BIT (U(1) << 1)

2
include/arch/aarch64/arch_helpers.h
View file

@ -442,6 +442,8 @@ DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
DEFINE_SYSREG_READ_FUNC(cntpct_el0)
DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
DEFINE_SYSREG_RW_FUNCS(vtcr_el2)
#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
CNTP_CTL_ENABLE_MASK)
#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \

5
plat/arm/board/fvp_r/fvp_r_bl1_context_mgmt.c
View file

@ -15,7 +15,7 @@
#include <plat/common/platform.h>
void cm_prepare_el2_exit(uint32_t security_state);
void cm_prepare_el2_exit(void);
/* Following contains the cpu context pointers. */
static void *bl1_cpu_context_ptr[2];
@ -81,6 +81,9 @@ void bl1_prepare_next_image(unsigned int image_id)
/* Allow platform to make change */
bl1_plat_set_ep_info(image_id, next_bl_ep);
/* Prepare context for the next EL */
cm_prepare_el2_exit();
/* Indicate that image is in execution state. */
desc->state = IMAGE_STATE_EXECUTED;

63
plat/arm/board/fvp_r/fvp_r_context_mgmt.c
View file

@ -4,25 +4,50 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/el3_runtime/pubsub_events.h>
#include <arch_helpers.h>
#include <platform_def.h>
/*******************************************************************************
* File contains EL2 equivalents of EL3 functions from
* .../lib/el3_runtime/aarch64/context_mgmt.c
******************************************************************************/
/*******************************************************************************
* Prepare the CPU system registers for first entry into secure or normal world
*
* The majority of the work needed is only for switching to non-secure, which
* is not available on v8-R64 cores, so this function is very simple.
******************************************************************************/
void cm_prepare_el2_exit(uint32_t security_state)
/************************************************************
* For R-class everything is in secure world.
* Prepare the CPU system registers for first entry into EL1
************************************************************/
void cm_prepare_el2_exit(void)
{
cm_el1_sysregs_context_restore(security_state);
cm_set_next_eret_context(security_state);
uint64_t hcr_el2 = 0U;
/*
* The use of ARMv8.3 pointer authentication (PAuth) is governed
* by fields in HCR_EL2, which trigger a 'trap to EL2' if not
* enabled. This register initialized at boot up, update PAuth
* bits.
*
* HCR_API_BIT: Set to one to disable traps to EL2 if lower ELs
* access PAuth registers
*
* HCR_APK_BIT: Set to one to disable traps to EL2 if lower ELs
* access PAuth instructions
*/
hcr_el2 = read_hcr_el2();
write_hcr_el2(hcr_el2 | HCR_API_BIT | HCR_APK_BIT);
/*
* Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN
* on reset and are set to zero except for field(s) listed below.
*
* CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to EL2
* if lower ELs accesses to the physical timer registers.
*
* CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to EL2
* if lower ELs access to the physical counter registers.
*/
write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT);
/*
* On Armv8-R, the EL1&0 memory system architecture is configurable
* as a VMSA or PMSA. All the fields architecturally UNKNOWN on reset
* and are set to zero except for field listed below.
*
* VCTR_EL2.MSA: Set to one to ensure the VMSA is enabled so that
* rich OS can boot.
*/
write_vtcr_el2(VTCR_RESET_VAL | VTCR_EL2_MSA);
}