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fix(rdn2): add LCA multichip data for RD-N2-Cfg2
This patch adds the routing table addresses required for LCA enablement on RD-N2-Cfg2. CMN on RD-N2-Cfg2 uses AXI Stream IDs to route LCA connections to the correct downstream tx_cxs_a4s port. The data programmed in the routing table are the A4S IDs of each chip. Change-Id: I46e558f3be7f0d51b768b7c5586f15e6bc517f3a Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
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1 changed files with 38 additions and 10 deletions
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@ -14,6 +14,10 @@
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#include <rdn2_ras.h>
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#include <rdn2_ras.h>
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#define RT_OWNER 0
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#define RT_OWNER 0
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#define A4SID_CHIP_0 0x0
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#define A4SID_CHIP_1 0x1
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#define A4SID_CHIP_2 0x2
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#define A4SID_CHIP_3 0x3
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#if defined(IMAGE_BL31)
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#if defined(IMAGE_BL31)
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#if (NRD_PLATFORM_VARIANT == 2)
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#if (NRD_PLATFORM_VARIANT == 2)
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@ -36,26 +40,50 @@ static const mmap_region_t rdn2mc_dynamic_mmap[] = {
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#if (NRD_PLATFORM_VARIANT == 2)
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#if (NRD_PLATFORM_VARIANT == 2)
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static struct gic600_multichip_data rdn2mc_multichip_data __init = {
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static struct gic600_multichip_data rdn2mc_multichip_data __init = {
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.base_addrs = {
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.base_addrs = {
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PLAT_ARM_GICD_BASE
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PLAT_ARM_GICD_BASE,
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#if NRD_CHIP_COUNT > 1
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PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
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#endif
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#if NRD_CHIP_COUNT > 2
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PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
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#endif
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#if NRD_CHIP_COUNT > 3
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PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
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#endif
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},
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},
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.rt_owner = RT_OWNER,
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.rt_owner = RT_OWNER,
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.chip_count = NRD_CHIP_COUNT,
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.chip_count = NRD_CHIP_COUNT,
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.chip_addrs = {
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.chip_addrs = {
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[RT_OWNER] = {
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{
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PLAT_ARM_GICD_BASE >> 16,
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A4SID_CHIP_0,
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A4SID_CHIP_1,
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A4SID_CHIP_2,
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A4SID_CHIP_3
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},
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#if NRD_CHIP_COUNT > 1
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#if NRD_CHIP_COUNT > 1
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(PLAT_ARM_GICD_BASE
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{
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+ NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
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A4SID_CHIP_0,
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A4SID_CHIP_1,
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A4SID_CHIP_2,
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A4SID_CHIP_3
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},
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#endif
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#endif
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#if NRD_CHIP_COUNT > 2
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#if NRD_CHIP_COUNT > 2
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(PLAT_ARM_GICD_BASE
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{
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+ NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
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A4SID_CHIP_0,
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A4SID_CHIP_1,
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A4SID_CHIP_2,
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A4SID_CHIP_3
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},
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#endif
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#endif
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#if NRD_CHIP_COUNT > 3
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#if NRD_CHIP_COUNT > 3
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(PLAT_ARM_GICD_BASE
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{
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+ NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
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A4SID_CHIP_0,
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#endif
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A4SID_CHIP_1,
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A4SID_CHIP_2,
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A4SID_CHIP_3
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}
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}
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#endif
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},
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},
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.spi_ids = {
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.spi_ids = {
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{PLAT_ARM_GICD_BASE,
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{PLAT_ARM_GICD_BASE,
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