Merge changes from topic "xlnx_fix_plat_invalid_entry" into integration

* changes:
  fix(versal): handle invalid entry point in cpu hotplug scenario
  fix(versal-net): handle invalid entry point in cpu hotplug scenario
  fix(zynqmp): handle invalid entry point in cpu hotplug scenario
This commit is contained in:
Joanna Farley 2025-03-26 11:13:57 +01:00 committed by TrustedFirmware Code Review
commit 2869609ca7
6 changed files with 57 additions and 2 deletions

View file

@ -63,6 +63,12 @@
# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE)
#endif #endif
/*******************************************************************************
* HIGH and LOW DDR MAX definitions
******************************************************************************/
#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
#define PLAT_DDR_HIGHMEM_MAX U(0x100000000)
/******************************************************************************* /*******************************************************************************
* TSP specific defines. * TSP specific defines.
******************************************************************************/ ******************************************************************************/

View file

@ -194,6 +194,18 @@ static void __dead2 versal_system_reset(void)
} }
} }
static int32_t versal_validate_ns_entrypoint(uint64_t ns_entrypoint)
{
int32_t ret = PSCI_E_SUCCESS;
if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) ||
((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) {
ret = PSCI_E_INVALID_ADDRESS;
}
return ret;
}
/** /**
* versal_pwr_domain_off() - This function performs actions to turn off core. * versal_pwr_domain_off() - This function performs actions to turn off core.
* @target_state: Targated state. * @target_state: Targated state.
@ -291,6 +303,7 @@ static const struct plat_psci_ops versal_nopmc_psci_ops = {
.pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish, .pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish,
.system_off = versal_system_off, .system_off = versal_system_off,
.system_reset = versal_system_reset, .system_reset = versal_system_reset,
.validate_ns_entrypoint = versal_validate_ns_entrypoint,
.validate_power_state = versal_validate_power_state, .validate_power_state = versal_validate_power_state,
.get_sys_suspend_power_state = versal_get_sys_suspend_power_state, .get_sys_suspend_power_state = versal_get_sys_suspend_power_state,
}; };

View file

@ -72,6 +72,12 @@
# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE)
#endif #endif
/*******************************************************************************
* HIGH and LOW DDR MAX definitions
******************************************************************************/
#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
#define PLAT_DDR_HIGHMEM_MAX U(0x100000000)
/******************************************************************************* /*******************************************************************************
* TSP specific defines. * TSP specific defines.
******************************************************************************/ ******************************************************************************/
@ -84,7 +90,6 @@
/******************************************************************************* /*******************************************************************************
* Platform specific page table and MMU setup constants * Platform specific page table and MMU setup constants
******************************************************************************/ ******************************************************************************/
#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U)

View file

@ -103,6 +103,18 @@ exit_label:
return; return;
} }
static int32_t versal_net_validate_ns_entrypoint(uint64_t ns_entrypoint)
{
int32_t ret = PSCI_E_SUCCESS;
if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) ||
((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) {
ret = PSCI_E_INVALID_ADDRESS;
}
return ret;
}
/** /**
* versal_net_system_reset() - This function sends the reset request to firmware * versal_net_system_reset() - This function sends the reset request to firmware
* for the system to reset. This function does not * for the system to reset. This function does not
@ -303,6 +315,7 @@ static const struct plat_psci_ops versal_net_nopmc_psci_ops = {
.pwr_domain_suspend_finish = versal_net_pwr_domain_suspend_finish, .pwr_domain_suspend_finish = versal_net_pwr_domain_suspend_finish,
.system_off = versal_net_system_off, .system_off = versal_net_system_off,
.system_reset = versal_net_system_reset, .system_reset = versal_net_system_reset,
.validate_ns_entrypoint = versal_net_validate_ns_entrypoint,
.validate_power_state = versal_net_validate_power_state, .validate_power_state = versal_net_validate_power_state,
.get_sys_suspend_power_state = versal_net_get_sys_suspend_power_state, .get_sys_suspend_power_state = versal_net_get_sys_suspend_power_state,
}; };

View file

@ -74,6 +74,12 @@
# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE)
#endif #endif
/*******************************************************************************
* HIGH and LOW DDR MAX definitions.
******************************************************************************/
#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
#define PLAT_DDR_HIGHMEM_MAX U(0x100000000)
/******************************************************************************* /*******************************************************************************
* TSP specific defines. * TSP specific defines.
******************************************************************************/ ******************************************************************************/
@ -87,7 +93,6 @@
* Platform specific page table and MMU setup constants * Platform specific page table and MMU setup constants
******************************************************************************/ ******************************************************************************/
#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
#define PLAT_OCM_BASE U(0xFFFC0000) #define PLAT_OCM_BASE U(0xFFFC0000)
#define PLAT_OCM_LIMIT U(0xFFFFFFFF) #define PLAT_OCM_LIMIT U(0xFFFFFFFF)

View file

@ -193,6 +193,18 @@ static void __dead2 zynqmp_system_reset(void)
} }
} }
static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint)
{
int32_t ret = PSCI_E_SUCCESS;
if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) ||
((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) {
ret = PSCI_E_INVALID_ADDRESS;
}
return ret;
}
static int32_t zynqmp_validate_power_state(uint32_t power_state, static int32_t zynqmp_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state) psci_power_state_t *req_state)
{ {
@ -235,6 +247,7 @@ static const struct plat_psci_ops zynqmp_psci_ops = {
.pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish,
.system_off = zynqmp_system_off, .system_off = zynqmp_system_off,
.system_reset = zynqmp_system_reset, .system_reset = zynqmp_system_reset,
.validate_ns_entrypoint = zynqmp_validate_ns_entrypoint,
.validate_power_state = zynqmp_validate_power_state, .validate_power_state = zynqmp_validate_power_state,
.get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state,
}; };