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https://github.com/ARM-software/arm-trusted-firmware.git
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SPMD: Adds partially supported EL2 registers.
This patch adds EL2 registers that are supported up to ARMv8.6. ARM_ARCH_MINOR has to specified to enable save/restore routine. Note: Following registers are still not covered in save/restore. * AMEVCNTVOFF0<n>_EL2 * AMEVCNTVOFF1<n>_EL2 * ICH_AP0R<n>_EL2 * ICH_AP1R<n>_EL2 * ICH_LR<n>_EL2 Change-Id: I4813f3243e56e21cb297b31ef549a4b38d4876e1 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
This commit is contained in:
Max Shvetsov
parent
28f39f02ad
commit
2825946e92
6 changed files with 455 additions and 412 deletions
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@ -68,7 +68,7 @@
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* registers are only 32-bits wide but are stored as 64-bit values for
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* convenience
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******************************************************************************/
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#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
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#define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
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#define CTX_SPSR_EL1 U(0x0)
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#define CTX_ELR_EL1 U(0x8)
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#define CTX_SCTLR_EL1 U(0x10)
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@ -136,7 +136,12 @@
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#endif /* CTX_INCLUDE_MTE_REGS */
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/*
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* S-EL2 register set
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* End of system registers.
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*/
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#define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END
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/*
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* EL2 register set
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*/
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#if CTX_INCLUDE_EL2_REGS
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@ -147,82 +152,104 @@
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* AMEVCNTVOFF1<n>_EL2
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* ICH_LR<n>_EL2
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*/
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#define CTX_ACTLR_EL2 (CTX_MTE_REGS_END + U(0x0))
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#define CTX_AFSR0_EL2 (CTX_MTE_REGS_END + U(0x8))
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#define CTX_AFSR1_EL2 (CTX_MTE_REGS_END + U(0x10))
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#define CTX_AMAIR_EL2 (CTX_MTE_REGS_END + U(0x18))
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#define CTX_CNTHCTL_EL2 (CTX_MTE_REGS_END + U(0x20))
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#define CTX_CNTHP_CTL_EL2 (CTX_MTE_REGS_END + U(0x28))
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#define CTX_CNTHP_CVAL_EL2 (CTX_MTE_REGS_END + U(0x30))
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#define CTX_CNTHP_TVAL_EL2 (CTX_MTE_REGS_END + U(0x38))
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#define CTX_CNTPOFF_EL2 (CTX_MTE_REGS_END + U(0x40))
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#define CTX_CNTVOFF_EL2 (CTX_MTE_REGS_END + U(0x48))
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#define CTX_CPTR_EL2 (CTX_MTE_REGS_END + U(0x50))
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#define CTX_DBGVCR32_EL2 (CTX_MTE_REGS_END + U(0x58))
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#define CTX_ELR_EL2 (CTX_MTE_REGS_END + U(0x60))
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#define CTX_ESR_EL2 (CTX_MTE_REGS_END + U(0x68))
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#define CTX_FAR_EL2 (CTX_MTE_REGS_END + U(0x70))
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#define CTX_FPEXC32_EL2 (CTX_MTE_REGS_END + U(0x78))
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#define CTX_HACR_EL2 (CTX_MTE_REGS_END + U(0x80))
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#define CTX_HAFGRTR_EL2 (CTX_MTE_REGS_END + U(0x88))
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#define CTX_HCR_EL2 (CTX_MTE_REGS_END + U(0x90))
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#define CTX_HDFGRTR_EL2 (CTX_MTE_REGS_END + U(0x98))
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#define CTX_HDFGWTR_EL2 (CTX_MTE_REGS_END + U(0xA0))
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#define CTX_HFGITR_EL2 (CTX_MTE_REGS_END + U(0xA8))
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#define CTX_HFGRTR_EL2 (CTX_MTE_REGS_END + U(0xB0))
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#define CTX_HFGWTR_EL2 (CTX_MTE_REGS_END + U(0xB8))
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#define CTX_HPFAR_EL2 (CTX_MTE_REGS_END + U(0xC0))
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#define CTX_HSTR_EL2 (CTX_MTE_REGS_END + U(0xC8))
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#define CTX_ICC_SRE_EL2 (CTX_MTE_REGS_END + U(0xD0))
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#define CTX_ICH_EISR_EL2 (CTX_MTE_REGS_END + U(0xD8))
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#define CTX_ICH_ELRSR_EL2 (CTX_MTE_REGS_END + U(0xE0))
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#define CTX_ICH_HCR_EL2 (CTX_MTE_REGS_END + U(0xE8))
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#define CTX_ICH_MISR_EL2 (CTX_MTE_REGS_END + U(0xF0))
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#define CTX_ICH_VMCR_EL2 (CTX_MTE_REGS_END + U(0xF8))
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#define CTX_ICH_VTR_EL2 (CTX_MTE_REGS_END + U(0x100))
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#define CTX_MAIR_EL2 (CTX_MTE_REGS_END + U(0x108))
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#define CTX_MDCR_EL2 (CTX_MTE_REGS_END + U(0x110))
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#define CTX_MPAM2_EL2 (CTX_MTE_REGS_END + U(0x118))
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#define CTX_MPAMHCR_EL2 (CTX_MTE_REGS_END + U(0x120))
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#define CTX_MPAMVPM0_EL2 (CTX_MTE_REGS_END + U(0x128))
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#define CTX_MPAMVPM1_EL2 (CTX_MTE_REGS_END + U(0x130))
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#define CTX_MPAMVPM2_EL2 (CTX_MTE_REGS_END + U(0x138))
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#define CTX_MPAMVPM3_EL2 (CTX_MTE_REGS_END + U(0x140))
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#define CTX_MPAMVPM4_EL2 (CTX_MTE_REGS_END + U(0x148))
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#define CTX_MPAMVPM5_EL2 (CTX_MTE_REGS_END + U(0x150))
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#define CTX_MPAMVPM6_EL2 (CTX_MTE_REGS_END + U(0x158))
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#define CTX_MPAMVPM7_EL2 (CTX_MTE_REGS_END + U(0x160))
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#define CTX_MPAMVPMV_EL2 (CTX_MTE_REGS_END + U(0x168))
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#define CTX_RMR_EL2 (CTX_MTE_REGS_END + U(0x170))
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#define CTX_SCTLR_EL2 (CTX_MTE_REGS_END + U(0x178))
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#define CTX_SPSR_EL2 (CTX_MTE_REGS_END + U(0x180))
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#define CTX_SP_EL2 (CTX_MTE_REGS_END + U(0x188))
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#define CTX_TCR_EL2 (CTX_MTE_REGS_END + U(0x190))
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#define CTX_TPIDR_EL2 (CTX_MTE_REGS_END + U(0x198))
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#define CTX_TTBR0_EL2 (CTX_MTE_REGS_END + U(0x1A0))
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#define CTX_VBAR_EL2 (CTX_MTE_REGS_END + U(0x1A8))
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#define CTX_VMPIDR_EL2 (CTX_MTE_REGS_END + U(0x1B0))
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#define CTX_VPIDR_EL2 (CTX_MTE_REGS_END + U(0x1B8))
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#define CTX_VTCR_EL2 (CTX_MTE_REGS_END + U(0x1C0))
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#define CTX_VTTBR_EL2 (CTX_MTE_REGS_END + U(0x1C8))
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#define CTX_ZCR_EL2 (CTX_MTE_REGS_END + U(0x1B0))
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#define CTX_EL2_SYSREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END)
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#define CTX_ACTLR_EL2 U(0x0)
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#define CTX_AFSR0_EL2 U(0x8)
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#define CTX_AFSR1_EL2 U(0x10)
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#define CTX_AMAIR_EL2 U(0x18)
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#define CTX_CNTHCTL_EL2 U(0x20)
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#define CTX_CNTHP_CTL_EL2 U(0x28)
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#define CTX_CNTHP_CVAL_EL2 U(0x30)
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#define CTX_CNTHP_TVAL_EL2 U(0x38)
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#define CTX_CNTVOFF_EL2 U(0x40)
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#define CTX_CPTR_EL2 U(0x48)
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#define CTX_DBGVCR32_EL2 U(0x50)
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#define CTX_ELR_EL2 U(0x58)
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#define CTX_ESR_EL2 U(0x60)
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#define CTX_FAR_EL2 U(0x68)
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#define CTX_FPEXC32_EL2 U(0x70)
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#define CTX_HACR_EL2 U(0x78)
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#define CTX_HCR_EL2 U(0x80)
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#define CTX_HPFAR_EL2 U(0x88)
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#define CTX_HSTR_EL2 U(0x90)
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#define CTX_ICC_SRE_EL2 U(0x98)
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#define CTX_ICH_HCR_EL2 U(0xa0)
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#define CTX_ICH_VMCR_EL2 U(0xa8)
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#define CTX_MAIR_EL2 U(0xb0)
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#define CTX_MDCR_EL2 U(0xb8)
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#define CTX_PMSCR_EL2 U(0xc0)
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#define CTX_SCTLR_EL2 U(0xc8)
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#define CTX_SPSR_EL2 U(0xd0)
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#define CTX_SP_EL2 U(0xd8)
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#define CTX_TCR_EL2 U(0xe0)
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#define CTX_TRFCR_EL2 U(0xe8)
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#define CTX_TTBR0_EL2 U(0xf0)
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#define CTX_VBAR_EL2 U(0xf8)
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#define CTX_VMPIDR_EL2 U(0x100)
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#define CTX_VPIDR_EL2 U(0x108)
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#define CTX_VTCR_EL2 U(0x110)
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#define CTX_VTTBR_EL2 U(0x118)
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// Only if MTE registers in use
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#define CTX_TFSR_EL2 U(0x120)
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// Only if ENABLE_MPAM_FOR_LOWER_ELS==1
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#define CTX_MPAM2_EL2 U(0x128)
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#define CTX_MPAMHCR_EL2 U(0x130)
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#define CTX_MPAMVPM0_EL2 U(0x138)
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#define CTX_MPAMVPM1_EL2 U(0x140)
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#define CTX_MPAMVPM2_EL2 U(0x148)
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#define CTX_MPAMVPM3_EL2 U(0x150)
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#define CTX_MPAMVPM4_EL2 U(0x158)
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#define CTX_MPAMVPM5_EL2 U(0x160)
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#define CTX_MPAMVPM6_EL2 U(0x168)
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#define CTX_MPAMVPM7_EL2 U(0x170)
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#define CTX_MPAMVPMV_EL2 U(0x178)
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// Starting with Armv8.6
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#define CTX_HAFGRTR_EL2 U(0x180)
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#define CTX_HDFGRTR_EL2 U(0x188)
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#define CTX_HDFGWTR_EL2 U(0x190)
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#define CTX_HFGITR_EL2 U(0x198)
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#define CTX_HFGRTR_EL2 U(0x1a0)
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#define CTX_HFGWTR_EL2 U(0x1a8)
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#define CTX_CNTPOFF_EL2 U(0x1b0)
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// Starting with Armv8.4
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#define CTX_CNTHPS_CTL_EL2 U(0x1b8)
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#define CTX_CNTHPS_CVAL_EL2 U(0x1c0)
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#define CTX_CNTHPS_TVAL_EL2 U(0x1c8)
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#define CTX_CNTHVS_CTL_EL2 U(0x1d0)
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#define CTX_CNTHVS_CVAL_EL2 U(0x1d8)
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#define CTX_CNTHVS_TVAL_EL2 U(0x1e0)
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#define CTX_CNTHV_CTL_EL2 U(0x1e8)
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#define CTX_CNTHV_CVAL_EL2 U(0x1f0)
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#define CTX_CNTHV_TVAL_EL2 U(0x1f8)
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#define CTX_CONTEXTIDR_EL2 U(0x200)
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#define CTX_SDER32_EL2 U(0x208)
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#define CTX_TTBR1_EL2 U(0x210)
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#define CTX_VDISR_EL2 U(0x218)
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#define CTX_VNCR_EL2 U(0x220)
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#define CTX_VSESR_EL2 U(0x228)
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#define CTX_VSTCR_EL2 U(0x230)
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#define CTX_VSTTBR_EL2 U(0x238)
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// Starting with Armv8.5
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#define CTX_SCXTNUM_EL2 U(0x240)
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/* Align to the next 16 byte boundary */
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#define CTX_EL2_REGS_END (CTX_MTE_REGS_END + U(0x1C0))
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#else
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#define CTX_EL2_REGS_END CTX_MTE_REGS_END
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#define CTX_EL2_SYSREGS_END U(0x250)
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#endif /* CTX_INCLUDE_EL2_REGS */
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/*
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* End of system registers.
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*/
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#define CTX_SYSREGS_END CTX_EL2_REGS_END
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the 'fp_regs'
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* structure at their correct offsets.
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******************************************************************************/
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#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END)
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#if CTX_INCLUDE_EL2_REGS
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# define CTX_FPREGS_OFFSET (CTX_EL2_SYSREGS_OFFSET + CTX_EL2_SYSREGS_END)
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#else
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# define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END)
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#endif
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#if CTX_INCLUDE_FPREGS
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#define CTX_FP_Q0 U(0x0)
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#define CTX_FP_Q1 U(0x10)
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@ -313,7 +340,10 @@
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/* Constants to determine the size of individual context structures */
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#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT)
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#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT)
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#define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT)
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#if CTX_INCLUDE_EL2_REGS
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# define CTX_EL2_SYSREGS_ALL (CTX_EL2_SYSREGS_END >> DWORD_SHIFT)
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#endif
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#if CTX_INCLUDE_FPREGS
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# define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT)
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#endif
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DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL);
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/*
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* AArch64 EL1/EL2 system register context structure for preserving the
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* AArch64 EL1 system register context structure for preserving the
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* architectural state during world switches.
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*/
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DEFINE_REG_STRUCT(sys_regs, CTX_SYSREG_ALL);
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DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL);
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/*
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* AArch64 EL2 system register context structure for preserving the
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* architectural state during world switches.
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*/
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#if CTX_INCLUDE_EL2_REGS
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DEFINE_REG_STRUCT(el2_sysregs, CTX_EL2_SYSREGS_ALL);
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#endif
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/*
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* AArch64 floating point register context structure for preserving
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typedef struct cpu_context {
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gp_regs_t gpregs_ctx;
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el3_state_t el3state_ctx;
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sys_regs_t sysregs_ctx;
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el1_sysregs_t el1_sysregs_ctx;
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#if CTX_INCLUDE_EL2_REGS
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el2_sysregs_t el2_sysregs_ctx;
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#endif
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#if CTX_INCLUDE_FPREGS
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fp_regs_t fpregs_ctx;
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#endif
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#if CTX_INCLUDE_FPREGS
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# define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx)
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#endif
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#define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx)
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#define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx)
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#if CTX_INCLUDE_EL2_REGS
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# define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx)
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#endif
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#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx)
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#define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx)
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#if CTX_INCLUDE_PAUTH_REGS
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*/
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CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
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assert_core_context_gp_offset_mismatch);
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CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \
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assert_core_context_sys_offset_mismatch);
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CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), \
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assert_core_context_el1_sys_offset_mismatch);
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#if CTX_INCLUDE_EL2_REGS
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CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), \
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assert_core_context_el2_sys_offset_mismatch);
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#endif
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#if CTX_INCLUDE_FPREGS
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CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \
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assert_core_context_fp_offset_mismatch);
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@ -464,12 +513,12 @@ CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \
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/*******************************************************************************
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* Function prototypes
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******************************************************************************/
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void el1_sysregs_context_save(sys_regs_t *regs);
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void el1_sysregs_context_restore(sys_regs_t *regs);
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void el1_sysregs_context_save(el1_sysregs_t *regs);
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void el1_sysregs_context_restore(el1_sysregs_t *regs);
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#if CTX_INCLUDE_EL2_REGS
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void el2_sysregs_context_save(sys_regs_t *regs);
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void el2_sysregs_context_restore(sys_regs_t *regs);
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void el2_sysregs_context_save(el2_sysregs_t *regs);
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void el2_sysregs_context_restore(el2_sysregs_t *regs);
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#endif
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#if CTX_INCLUDE_FPREGS
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