From 2716bd33e318821c373b3d4dce88110a340a740d Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 19 Aug 2022 16:21:29 +0100 Subject: [PATCH] feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel The existing DT files for the base FVP model are having some issues, that lead to warnings reported by the device tree compiler. Those (and many other issues around (updated) DT binding compliance) were fixed in the Linux kernel tree, so let's sync those files back into TF-A. We cannot copy the files "as is" for now, since we rely on certain custom properties to be added (max-pwr-lvl in the PSCI node, SDEI nodes, etc). Merge in the changed parts of the Linux kernel DT (from Linux v6.0-rc1), and rework the base file to allow including the motherboard.dtsi unchanged. This should make any future update less painful. As this also affects the FVP VE boards (Cortex-A7 and Cortex-A5), since they share the motherboard include file, fix them up as well. Change-Id: I4f74d05e5583747f8849e32f246f74aeec7a9c60 Signed-off-by: Andre Przywara --- fdts/fvp-base-psci-common.dtsi | 91 +++---- fdts/fvp-ve-Cortex-A5x1.dts | 43 ++-- fdts/fvp-ve-Cortex-A7x1.dts | 38 ++- fdts/rtsm_ve-motherboard.dtsi | 447 +++++++++++++++++---------------- 4 files changed, 320 insertions(+), 299 deletions(-) diff --git a/fdts/fvp-base-psci-common.dtsi b/fdts/fvp-base-psci-common.dtsi index 69af15a0e..cf75c9550 100644 --- a/fdts/fvp-base-psci-common.dtsi +++ b/fdts/fvp-base-psci-common.dtsi @@ -1,7 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * ARM Ltd. Fast Models * - * SPDX-License-Identifier: BSD-3-Clause + * Architecture Envelope Model (AEM) ARMv8-A + * ARMAEMv8AMPCT + * + * RTSM_VE_AEMv8A.lisa + * + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. */ #include @@ -12,6 +18,8 @@ #define SDEI_NORMAL 0x70 #define HIGHEST_SEC 0 +#include "rtsm_ve-motherboard.dtsi" + / { model = "FVP Base"; compatible = "arm,fvp-base", "arm,vexpress"; @@ -138,16 +146,26 @@ #endif }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Chipselect 2,00000000 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0x00000000 0x18000000 0 0x00800000>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <100000000>; }; @@ -167,24 +185,22 @@ pmu { compatible = "arm,armv8-pmuv3"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; + interrupts = , + , + , + ; }; - smb@0 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; + panel { + compatible = "arm,rtsm-display"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + bus@8000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -230,30 +246,5 @@ <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - - #include "rtsm_ve-motherboard.dtsi" - }; - - panels { - panel { - compatible = "panel"; - mode = "XVGA"; - refresh = <60>; - xres = <1024>; - yres = <768>; - pixclock = <15748>; - left_margin = <152>; - right_margin = <48>; - upper_margin = <23>; - lower_margin = <3>; - hsync_len = <104>; - vsync_len = <4>; - sync = <0>; - vmode = "FB_VMODE_NONINTERLACED"; - tim2 = "TIM2_BCD", "TIM2_IPC"; - cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; - caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; - bpp = <16>; - }; }; }; diff --git a/fdts/fvp-ve-Cortex-A5x1.dts b/fdts/fvp-ve-Cortex-A5x1.dts index 534c3a51f..23a6e1382 100644 --- a/fdts/fvp-ve-Cortex-A5x1.dts +++ b/fdts/fvp-ve-Cortex-A5x1.dts @@ -8,6 +8,8 @@ /dts-v1/; +#include "rtsm_ve-motherboard.dtsi" + / { model = "V2P-CA5s"; compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; @@ -32,6 +34,20 @@ reg = <0 0x80000000 0x1000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + /* Chipselect 2,00000000 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0 0x18000000 0x00800000>; + no-map; + }; + }; + hdlcd@2a110000 { compatible = "arm,hdlcd"; reg = <0 0x2a110000 0x1000>; @@ -60,10 +76,7 @@ <0 0x2c000100 0x100>; }; - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - + mcc { oscclk0: osc@0 { /* CPU and internal AXI reference clock */ compatible = "arm,vexpress-osc"; @@ -119,18 +132,16 @@ }; }; - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; + panel { + compatible = "arm,rtsm-display"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + bus@8000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -152,7 +163,5 @@ <0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, <0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, <0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - - #include "rtsm_ve-motherboard.dtsi" }; }; diff --git a/fdts/fvp-ve-Cortex-A7x1.dts b/fdts/fvp-ve-Cortex-A7x1.dts index 21e3365ad..6ec6adb60 100644 --- a/fdts/fvp-ve-Cortex-A7x1.dts +++ b/fdts/fvp-ve-Cortex-A7x1.dts @@ -8,6 +8,8 @@ /dts-v1/; +#include "rtsm_ve-motherboard.dtsi" + / { model = "V2F-1XV7 Cortex-A7x1 SMM"; compatible = "arm,vexpress,v2f-1xv7", "arm,vexpress"; @@ -31,6 +33,20 @@ reg = <0 0x80000000 0x80000000>; /* 2GB @ 2GB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + /* Chipselect 2,00000000 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0 0x18000000 0x00800000>; + no-map; + }; + }; + gic: interrupt-controller@2c001000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; @@ -51,18 +67,16 @@ clock-output-names = "smclk"; }; - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; + panel { + compatible = "arm,rtsm-display"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + bus@8000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -84,7 +98,5 @@ <0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, <0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, <0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - - #include "rtsm_ve-motherboard.dtsi" }; }; diff --git a/fdts/rtsm_ve-motherboard.dtsi b/fdts/rtsm_ve-motherboard.dtsi index 7851fe198..0a824b349 100644 --- a/fdts/rtsm_ve-motherboard.dtsi +++ b/fdts/rtsm_ve-motherboard.dtsi @@ -1,251 +1,260 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * ARM Ltd. Fast Models * - * SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2012-2022 ARM Ltd. + * + * Versatile Express (VE) system model + * Motherboard component + * + * VEMotherBoard.lisa */ +/ { + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; - motherboard { - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + v2m_fixed_3v3: v2m-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + + bus@8000000 { + compatible = "simple-bus"; + #address-cells = <2>; #size-cells = <1>; - ranges; + ranges = <0 0x8000000 0 0x8000000 0x18000000>; - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; - - vram@2,00000000 { - compatible = "arm,vexpress-vram"; - reg = <2 0x00000000 0x00800000>; - }; - - ethernet@2,02000000 { - compatible = "smsc,lan91c111"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - iofpga@3,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; + motherboard-bus@8000000 { + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; - ranges = <0 3 0 0x200000>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - gpio-controller; - #gpio-cells = <2>; + flash@0 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; }; - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + ethernet@202000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; }; - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&v2m_clk24mhz>; - clock-names = "apb_pclk"; - }; + iofpga-bus@300000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x210000>; - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_sysreg 0 0>; - wp-gpios = <&v2m_sysreg 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "mclk", "apb_pclk"; - }; + v2m_sysreg: sysreg@10000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; + v2m_sysctl: sysctl@20000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + }; - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; + aaci@40000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; - v2m_serial0: uart@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; + mmc@50000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9>, <10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "mclk", "apb_pclk"; + }; - v2m_serial1: uart@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; + kmi@60000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; - v2m_serial2: uart@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; + kmi@70000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; - v2m_serial3: uart@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; + v2m_serial0: serial@90000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; - clock-names = "wdogclk", "apb_pclk"; - }; + v2m_serial1: serial@a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; + v2m_serial2: serial@b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; + v2m_serial3: serial@c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&v2m_clk24mhz>; - clock-names = "apb_pclk"; - }; + watchdog@f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdog_clk", "apb_pclk"; + }; - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; - clock-names = "clcdclk", "apb_pclk"; - mode = "XVGA"; - use_dma = <0>; - framebuffer = <0x18000000 0x00180000>; - }; + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; - virtio_block@130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x1000>; - interrupts = <0x2a>; - }; - }; + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; - v2m_fixed_3v3: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + virtio@130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x200>; + interrupts = <42>; + }; - mcc { - compatible = "arm,vexpress,config-bus", "simple-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; - v2m_oscclk1: osc { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; + clock-names = "clcdclk", "apb_pclk"; + memory-region = <&vram>; - /* - * Not supported in FVP models - * - * reset@0 { - * compatible = "arm,vexpress-reset"; - * arm,vexpress-sysreg,func = <5 0>; - * }; - */ - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - /* - * Not used - Superseded by PSCI sys_poweroff - * - * shutdown@0 { - * compatible = "arm,vexpress-shutdown"; - * arm,vexpress-sysreg,func = <8 0>; - * }; - */ - - /* - * Not used - Superseded by PSCI sys_reset - * - * reboot@0 { - * compatible = "arm,vexpress-reboot"; - * arm,vexpress-sysreg,func = <9 0>; - * }; - */ - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; + port { + clcd_pads: endpoint { + remote-endpoint = <&panel_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; }; }; }; +};