From 94a4383a2b7de555ac68fc4f571d08105cdb3296 Mon Sep 17 00:00:00 2001 From: Lokesh B V <Lokesh.BV@Arm.com> Date: Tue, 11 Feb 2025 18:46:20 +0530 Subject: [PATCH] fix(neoverse-rd): initialize CNTFRQ_EL0 for RESET_TO_BL31 When RESET_TO_BL31 was enabled, CNTFRQ_EL0 was left uninitialized, leading to incorrect system counter frequency settings. This impacted timer-dependent components, such as SMMUv3, causing initialization failures and unpredictable behavior. To fix this, CNTFRQ_EL0 is now explicitly set using plat_get_syscnt_freq2(), ensuring the correct system timer frequency and proper initialization of dependent components. Signed-off-by: Lokesh B V <Lokesh.BV@Arm.com> Change-Id: I808b17d25c87c4dce1bc2c8171a800b69b5c2908 --- plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c index d3038ec4e..2dd8b452a 100644 --- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c +++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c @@ -154,6 +154,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, nrd_plat_info.config_id = plat_arm_nrd_get_config_id(); nrd_plat_info.multi_chip_mode = plat_arm_nrd_get_multi_chip_mode(); +#if RESET_TO_BL31 +#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER) + /* Set the counter frequency for the generic timer */ + write_cntfrq_el0(plat_get_syscnt_freq2()); +#endif +#endif /* RESET_TO_BL31 */ + /* Initialize generic timer */ generic_delay_timer_init();