From 26437afde1e7c16a5a05b8c7e0bb062efe63c3cf Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 17:00:11 -0600 Subject: [PATCH] fix(cpus): workaround for Cortex-A715 erratum 3699560 Cortex-A715 erratum 3699560 that applies to all revisions <= r1p3 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2148827/latest/ Change-Id: I183aa921b4b6f715d64eb6b70809de2566017d31 Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/cortex_a715.h | 6 +++++- lib/cpus/aarch64/cortex_a715.S | 8 +++++++- lib/cpus/cpu-ops.mk | 5 +++++ lib/cpus/errata_common.c | 8 ++++++++ 5 files changed, 29 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index ed0988555..47fa95568 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -960,6 +960,10 @@ For Cortex-A715, the following errata build flags are defined : Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1. It is fixed in r1p2. +- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to + Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, + r1p2, r1p3. It is still open. + For Cortex-A720, the following errata build flags are defined : - ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to diff --git a/include/lib/cpus/aarch64/cortex_a715.h b/include/lib/cpus/aarch64/cortex_a715.h index c7f50db34..e9bd886f5 100644 --- a/include/lib/cpus/aarch64/cortex_a715.h +++ b/include/lib/cpus/aarch64/cortex_a715.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -38,4 +38,8 @@ #define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#ifndef __ASSEMBLER__ +long check_erratum_cortex_a715_3699560(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_A715_H */ diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S index 8c9988da0..fbc73eda3 100644 --- a/lib/cpus/aarch64/cortex_a715.S +++ b/lib/cpus/aarch64/cortex_a715.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,8 @@ #error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_a715_3699560 + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 #endif /* WORKAROUND_CVE_2022_23960 */ @@ -127,6 +129,10 @@ workaround_reset_end cortex_a715, CVE(2022, 23960) check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +add_erratum_entry cortex_a715, ERRATUM(3699560), ERRATA_A715_3699560, NO_APPLY_AT_RESET + +check_erratum_ls cortex_a715, ERRATUM(3699560), CPU_REV(1, 3) + cpu_reset_func_start cortex_a715 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 81ce13108..0e5e24c69 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -989,6 +989,11 @@ CPU_FLAG_LIST += ERRATA_A715_2561034 # only to revision r0p0, r1p0 and r1p1. It is fixed in r1p2. CPU_FLAG_LIST += ERRATA_A715_2728106 +# Flag to apply erratum 3699560 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r1p2, r1p3 +# of the Cortex-A715 cpu and is still open. +CPU_FLAG_LIST += ERRATA_A715_3699560 + # Flag to apply erratum 2792132 workaround during reset. This erratum applies # to revisions r0p0 and r0p1. It is fixed in r0p2. CPU_FLAG_LIST += ERRATA_A720_2792132 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index 7c4db4648..08f878606 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,13 @@ bool errata_ich_vmcr_el2_applies(void) break; #endif /* ERRATA_A710_3701772 */ +#if ERRATA_A715_3699560 + case EXTRACT_PARTNUM(CORTEX_A715_MIDR): + if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES) + return true; + break; +#endif /* ERRATA_A715_3699560 */ + default: break; }