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Enable data caches early with hardware-assisted coherency

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At present, warm-booted CPUs keep their caches disabled when enabling
MMU, and remains so until they enter coherency later.

On systems with hardware-assisted coherency, for which
HW_ASSISTED_COHERENCY build flag would be enabled, warm-booted CPUs can
have both caches and MMU enabled at once.

Change-Id: Icb0adb026e01aecf34beadf49c88faa9dd368327
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
This commit is contained in:
Jeenu Viswambharan 2017-01-05 10:37:21 +00:00
parent 3c251af392
commit 25a93f7cd1
2 changed files with 42 additions and 34 deletions
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39
bl31/aarch64/bl31_entrypoint.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
@ -180,24 +180,29 @@ func bl31_warm_entrypoint
_init_c_runtime=0 \ _init_c_runtime=0 \
_exception_vectors=runtime_exceptions _exception_vectors=runtime_exceptions
/* -------------------------------------------- /*
* Enable the MMU with the DCache disabled. It * We're about to enable MMU and participate in PSCI state coordination.
* is safe to use stacks allocated in normal *
* memory as a result. All memory accesses are * The PSCI implementation invokes platform routines that enable CPUs to
* marked nGnRnE when the MMU is disabled. So * participate in coherency. On a system where CPUs are not
* all the stack writes will make it to memory. * cache-coherent out of reset, having caches enabled until such time
* All memory accesses are marked Non-cacheable * might lead to coherency issues (resulting from stale data getting
* when the MMU is enabled but D$ is disabled. * speculatively fetched, among others). Therefore we keep data caches
* So used stack memory is guaranteed to be * disabled while enabling the MMU, thereby forcing data accesses to
* visible immediately after the MMU is enabled * have non-cacheable, nGnRnE attributes (these will always be coherent
* Enabling the DCache at the same time as the * with main memory).
* MMU can lead to speculatively fetched and *
* possibly stale stack memory being read from * On systems with hardware-assisted coherency, where CPUs are expected
* other caches. This can lead to coherency * to be cache-coherent out of reset without needing explicit software
* issues. * intervention, PSCI need not invoke platform routines to enter
* -------------------------------------------- * coherency (as CPUs already are); and there's no reason to have caches
* disabled either.
*/ */
#if HW_ASSISTED_COHERENCY
mov x0, #0
#else
mov x0, #DISABLE_DCACHE mov x0, #DISABLE_DCACHE
#endif
bl bl31_plat_enable_mmu bl bl31_plat_enable_mmu
bl psci_warmboot_entrypoint bl psci_warmboot_entrypoint

37
bl32/sp_min/aarch32/entrypoint.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
@ -231,24 +231,27 @@ func sp_min_warm_entrypoint
_init_c_runtime=0 \ _init_c_runtime=0 \
_exception_vectors=sp_min_vector_table _exception_vectors=sp_min_vector_table
/* -------------------------------------------- /*
* Enable the MMU with the DCache disabled. It * We're about to enable MMU and participate in PSCI state coordination.
* is safe to use stacks allocated in normal *
* memory as a result. All memory accesses are * The PSCI implementation invokes platform routines that enable CPUs to
* marked nGnRnE when the MMU is disabled. So * participate in coherency. On a system where CPUs are not
* all the stack writes will make it to memory. * cache-coherent out of reset, having caches enabled until such time
* All memory accesses are marked Non-cacheable * might lead to coherency issues (resulting from stale data getting
* when the MMU is enabled but D$ is disabled. * speculatively fetched, among others). Therefore we keep data caches
* So used stack memory is guaranteed to be * disabled while enabling the MMU, thereby forcing data accesses to
* visible immediately after the MMU is enabled * have non-cacheable, nGnRnE attributes (these will always be coherent
* Enabling the DCache at the same time as the * with main memory).
* MMU can lead to speculatively fetched and *
* possibly stale stack memory being read from * On systems where CPUs are cache-coherent out of reset, however, PSCI
* other caches. This can lead to coherency * need not invoke platform routines to enter coherency (as CPUs already
* issues. * are), and there's no reason to have caches disabled either.
* --------------------------------------------
*/ */
#if HW_ASSISTED_COHERENCY
mov r0, #0
#else
mov r0, #DISABLE_DCACHE mov r0, #DISABLE_DCACHE
#endif
bl bl32_plat_enable_mmu bl bl32_plat_enable_mmu
bl sp_min_warm_boot bl sp_min_warm_boot