From 2590e819ebccc2223b68b6ed1a4e6145f79e2ea0 Mon Sep 17 00:00:00 2001 From: Boyan Karatotev Date: Mon, 25 Nov 2024 10:14:26 +0000 Subject: [PATCH] perf(mpmm): greatly simplify MPMM enablement MPMM is a core-specific microarchitectural feature. It has been present in every Arm core since the Cortex-A510 and has been implemented in exactly the same way. Despite that, it is enabled more like an architectural feature with a top level enable flag. This utilised the identical implementation. This duality has left MPMM in an awkward place, where its enablement should be generic, like an architectural feature, but since it is not, it should also be core-specific if it ever changes. One choice to do this has been through the device tree. This has worked just fine so far, however, recent implementations expose a weakness in that this is rather slow - the device tree has to be read, there's a long call stack of functions with many branches, and system registers are read. In the hot path of PSCI CPU powerdown, this has a significant and measurable impact. Besides it being a rather large amount of code that is difficult to understand. Since MPMM is a microarchitectural feature, its correct placement is in the reset function. The essence of the current enablement is to write CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C enablement with an assembly macro in each CPU's reset function achieves the same effect with just a single close branch and a grand total of 6 instructions (versus the old 2 branches and 32 instructions). Having done this, the device tree entry becomes redundant. Should a core that doesn't support MPMM arise, this can cleanly be handled in the reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks mechanisms become obsolete and are removed. Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf Signed-off-by: Boyan Karatotev --- Makefile | 2 - bl31/bl31.mk | 5 -- docs/about/maintainers.rst | 3 +- docs/components/fconf/index.rst | 1 - docs/components/fconf/mpmm-bindings.rst | 48 -------------- docs/components/mpmm.rst | 11 +--- docs/getting_started/build-options.rst | 4 -- fdts/tc-base.dtsi | 8 --- fdts/tc2.dts | 6 -- include/arch/aarch64/arch.h | 6 +- include/lib/cpus/aarch64/cpu_macros.S | 17 +++++ include/lib/fconf/fconf_mpmm_getter.h | 20 ------ include/lib/mpmm/mpmm.h | 57 ---------------- lib/cpus/aarch64/cortex_a510.S | 23 +++---- lib/cpus/aarch64/cortex_a520.S | 1 + lib/cpus/aarch64/cortex_a710.S | 1 + lib/cpus/aarch64/cortex_a715.S | 1 + lib/cpus/aarch64/cortex_a720.S | 1 + lib/cpus/aarch64/cortex_a720_ae.S | 1 + lib/cpus/aarch64/cortex_a725.S | 1 + lib/cpus/aarch64/cortex_alto.S | 1 + lib/cpus/aarch64/cortex_arcadia.S | 1 + lib/cpus/aarch64/cortex_gelas.S | 1 + lib/cpus/aarch64/cortex_x2.S | 1 + lib/cpus/aarch64/cortex_x3.S | 1 + lib/cpus/aarch64/cortex_x4.S | 1 + lib/cpus/aarch64/cortex_x925.S | 1 + lib/cpus/aarch64/nevis.S | 1 + lib/cpus/aarch64/travis.S | 1 + lib/extensions/amu/aarch64/amu.c | 8 --- lib/fconf/fconf.mk | 5 +- lib/fconf/fconf_mpmm_getter.c | 80 ----------------------- lib/mpmm/mpmm.c | 86 ------------------------- lib/mpmm/mpmm.mk | 29 --------- make_helpers/defaults.mk | 3 - plat/arm/board/tc/platform.mk | 1 - 36 files changed, 46 insertions(+), 392 deletions(-) delete mode 100644 docs/components/fconf/mpmm-bindings.rst delete mode 100644 include/lib/fconf/fconf_mpmm_getter.h delete mode 100644 include/lib/mpmm/mpmm.h delete mode 100644 lib/fconf/fconf_mpmm_getter.c delete mode 100644 lib/mpmm/mpmm.c delete mode 100644 lib/mpmm/mpmm.mk diff --git a/Makefile b/Makefile index 5682f93f9..1e32ddec3 100644 --- a/Makefile +++ b/Makefile @@ -1252,7 +1252,6 @@ $(eval $(call assert_booleans,\ PSA_FWU_METADATA_FW_STORE_DESC \ ENABLE_MPMM \ FEAT_PABANDON \ - ENABLE_MPMM_FCONF \ FEATURE_DETECTION \ TRNG_SUPPORT \ ENABLE_ERRATA_ALL \ @@ -1454,7 +1453,6 @@ $(eval $(call add_defines,\ ENABLE_FEAT_HCX \ ENABLE_MPMM \ FEAT_PABANDON \ - ENABLE_MPMM_FCONF \ ENABLE_FEAT_FGT \ ENABLE_FEAT_FGT2 \ ENABLE_FEAT_FPMR \ diff --git a/bl31/bl31.mk b/bl31/bl31.mk index 9b2b139ae..e39091528 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -24,7 +24,6 @@ ifeq (${SPM_MM},1) endif include lib/extensions/amu/amu.mk -include lib/mpmm/mpmm.mk ifeq (${SPMC_AT_EL3},1) $(info Including EL3 SPMC makefile) @@ -114,10 +113,6 @@ ifneq (${ENABLE_FEAT_TCR2},0) BL31_SOURCES += lib/extensions/tcr/tcr2.c endif -ifeq (${ENABLE_MPMM},1) -BL31_SOURCES += ${MPMM_SOURCES} -endif - ifneq (${ENABLE_SME_FOR_NS},0) BL31_SOURCES += lib/extensions/sme/sme.c endif diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst index 210ae7e98..7914f6df3 100644 --- a/docs/about/maintainers.rst +++ b/docs/about/maintainers.rst @@ -447,8 +447,7 @@ Max Power Mitigation Mechanism (MPMM) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Chris Kay :|G|: `CJKay`_ -:|F|: include/lib/mpmm/ -:|F|: lib/mpmm/ +:|F|: include/lib/cpus/aarch64/cpu_macros.S Granule Protection Tables Library (GPT-RME) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/components/fconf/index.rst b/docs/components/fconf/index.rst index b8b4519e3..c10f1ea67 100644 --- a/docs/components/fconf/index.rst +++ b/docs/components/fconf/index.rst @@ -146,5 +146,4 @@ Properties binding information fconf_properties amu-bindings - mpmm-bindings tb_fw_bindings diff --git a/docs/components/fconf/mpmm-bindings.rst b/docs/components/fconf/mpmm-bindings.rst deleted file mode 100644 index d3cc857a8..000000000 --- a/docs/components/fconf/mpmm-bindings.rst +++ /dev/null @@ -1,48 +0,0 @@ -Maximum Power Mitigation Mechanism (MPMM) Bindings -================================================== - -|MPMM| support cannot be determined at runtime by the firmware. Instead, these -DTB bindings allow the platform to communicate per-core support for |MPMM| via -the ``HW_CONFIG`` device tree blob. - -Bindings -^^^^^^^^ - -.. contents:: - :local: - -``/cpus/cpus/cpu*`` node properties -""""""""""""""""""""""""""""""""""" - -The ``cpu`` node has been augmented to allow the platform to indicate support -for |MPMM| on a given core. - -+-------------------+-------+-------------+------------------------------------+ -| Property name | Usage | Value type | Description | -+===================+=======+=============+====================================+ -| ``supports-mpmm`` | O | ```` | If present, indicates that |MPMM| | -| | | | is available on this core. | -+-------------------+-------+-------------+------------------------------------+ - -Example -^^^^^^^ - -An example system offering two cores, one with support for |MPMM| and one -without, can be described as follows: - -.. code-block:: - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0@00000 { - ... - - supports-mpmm; - }; - - cpu1@00100 { - ... - }; - } diff --git a/docs/components/mpmm.rst b/docs/components/mpmm.rst index 1b1c6d8c7..aaa948131 100644 --- a/docs/components/mpmm.rst +++ b/docs/components/mpmm.rst @@ -8,16 +8,7 @@ assist in |SoC| processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. -|MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence -of |MPMM| cannot be determined at runtime by the firmware, and therefore the -platform must expose this information through one of two possible mechanisms: - -- |FCONF|, controlled by the ``ENABLE_MPMM_FCONF`` build option. -- A platform implementation of the ``plat_mpmm_topology`` function (the - default). - -See :ref:`Maximum Power Mitigation Mechanism (MPMM) Bindings` for documentation -on the |FCONF| device tree bindings. +|MPMM| is enabled on a per-core basis by the EL3 runtime firmware. .. warning:: diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 8840e7fda..4846d328a 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -532,10 +532,6 @@ Common build options introduces a performance penalty. Once this is removed, this option will be removed and the feature will be enabled by default. Defaults to ``0``. -- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which - allows platforms with cores supporting MPMM to describe them via the - ``HW_CONFIG`` device tree blob. Default is 0. - - ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) support within generic code in TF-A. This option is currently only supported in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index fc0b3b642..942cf75ef 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -135,7 +135,6 @@ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = ; amu = <&amu>; - supports-mpmm; }; CPU1:cpu@100 { @@ -147,7 +146,6 @@ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = ; amu = <&amu>; - supports-mpmm; }; CPU2:cpu@200 { @@ -157,7 +155,6 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; amu = <&amu>; - supports-mpmm; }; CPU3:cpu@300 { @@ -167,7 +164,6 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; amu = <&amu>; - supports-mpmm; }; CPU4:cpu@400 { @@ -179,7 +175,6 @@ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = ; amu = <&amu>; - supports-mpmm; }; CPU5:cpu@500 { @@ -191,7 +186,6 @@ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = ; amu = <&amu>; - supports-mpmm; }; CPU6:cpu@600 { @@ -201,7 +195,6 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; amu = <&amu>; - supports-mpmm; }; CPU7:cpu@700 { @@ -211,7 +204,6 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; amu = <&amu>; - supports-mpmm; }; }; diff --git a/fdts/tc2.dts b/fdts/tc2.dts index 8aa77ce86..0f92294f7 100644 --- a/fdts/tc2.dts +++ b/fdts/tc2.dts @@ -124,7 +124,6 @@ clocks = <&scmi_dvfs 1>; capacity-dmips-mhz = ; amu = <&amu>; - supports-mpmm; }; CPU9:cpu@900 { @@ -135,7 +134,6 @@ clocks = <&scmi_dvfs 2>; capacity-dmips-mhz = ; amu = <&amu>; - supports-mpmm; }; CPU10:cpu@A00 { @@ -146,7 +144,6 @@ clocks = <&scmi_dvfs 2>; capacity-dmips-mhz = ; amu = <&amu>; - supports-mpmm; }; CPU11:cpu@B00 { @@ -157,7 +154,6 @@ clocks = <&scmi_dvfs 2>; capacity-dmips-mhz = ; amu = <&amu>; - supports-mpmm; }; CPU12:cpu@C00 { @@ -168,7 +164,6 @@ clocks = <&scmi_dvfs 3>; capacity-dmips-mhz = ; amu = <&amu>; - supports-mpmm; }; CPU13:cpu@D00 { @@ -179,7 +174,6 @@ clocks = <&scmi_dvfs 3>; capacity-dmips-mhz = ; amu = <&amu>; - supports-mpmm; }; #endif }; diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index b1d1f0965..85b33aaa1 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1560,12 +1560,10 @@ ******************************************************************************/ #define CPUPPMCR_EL3 S3_6_C15_C2_0 -#define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) -#define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) +#define CPUPPMCR_EL3_MPMMPINCTL_BIT BIT(0) #define CPUMPMMCR_EL3 S3_6_C15_C2_1 -#define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) -#define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) +#define CPUMPMMCR_EL3_MPMM_EN_BIT BIT(0) /* alternative system register encoding for the "sb" speculation barrier */ #define SYSREG_SB S0_3_C3_C0_7 diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index f3df59568..a43746f7a 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -631,4 +631,21 @@ endfunc \_cpu\()_reset_func .endm +/* + * Helper macro that enables Maximum Power Mitigation Mechanism (MPMM) on + * compatible Arm cores. + * + * Clobbers x0. + */ +.macro enable_mpmm +#if ENABLE_MPMM + mrs x0, CPUPPMCR_EL3 + /* if CPUPPMCR_EL3.MPMMPINCTL != 0, skip enabling MPMM */ + ands x0, x0, CPUPPMCR_EL3_MPMMPINCTL_BIT + b.ne 1f + sysreg_bit_set CPUPPMCR_EL3, CPUMPMMCR_EL3_MPMM_EN_BIT + 1: +#endif +.endm + #endif /* CPU_MACROS_S */ diff --git a/include/lib/fconf/fconf_mpmm_getter.h b/include/lib/fconf/fconf_mpmm_getter.h deleted file mode 100644 index 50d991a2f..000000000 --- a/include/lib/fconf/fconf_mpmm_getter.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2021, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef FCONF_MPMM_GETTER_H -#define FCONF_MPMM_GETTER_H - -#include - -#define mpmm__config_getter(id) fconf_mpmm_config.id - -struct fconf_mpmm_config { - const struct mpmm_topology *topology; -}; - -extern struct fconf_mpmm_config fconf_mpmm_config; - -#endif /* FCONF_MPMM_GETTER_H */ diff --git a/include/lib/mpmm/mpmm.h b/include/lib/mpmm/mpmm.h deleted file mode 100644 index 955c530e8..000000000 --- a/include/lib/mpmm/mpmm.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2021, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef MPMM_H -#define MPMM_H - -#include - -#include - -/* - * Enable the Maximum Power Mitigation Mechanism. - * - * This function will enable MPMM for the current core. The AMU counters - * representing the MPMM gears must have been configured and enabled prior to - * calling this function. - */ -void mpmm_enable(void); - -/* - * MPMM core data. - * - * This structure represents per-core data retrieved from the hardware - * configuration device tree. - */ -struct mpmm_core { - /* - * Whether MPMM is supported. - * - * Cores with support for MPMM offer one or more auxiliary AMU counters - * representing MPMM gears. - */ - bool supported; -}; - -/* - * MPMM topology. - * - * This topology structure describes the system-wide representation of the - * information retrieved from the hardware configuration device tree. - */ -struct mpmm_topology { - struct mpmm_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */ -}; - -#if !ENABLE_MPMM_FCONF -/* - * Retrieve the platform's MPMM topology. A `NULL` return value is treated as a - * non-fatal error, in which case MPMM will not be enabled for any core. - */ -const struct mpmm_topology *plat_mpmm_topology(void); -#endif /* ENABLE_MPMM_FCONF */ - -#endif /* MPMM_H */ diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index cbeeb2b7e..81a227b95 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -111,25 +111,11 @@ workaround_reset_end cortex_a510, ERRATUM(2218950) check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0) - /* -------------------------------------------------- - * This workaround is not a typical errata fix. MPMM - * is disabled here, but this conflicts with the BL31 - * MPMM support. So in addition to simply disabling - * the feature, a flag is set in the MPMM library - * indicating that it should not be enabled even if - * ENABLE_MPMM=1. - * -------------------------------------------------- - */ workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311 /* Disable MPMM */ mrs x0, CPUMPMMCR_EL3 bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ msr CPUMPMMCR_EL3, x0 - -#if ENABLE_MPMM && IMAGE_BL31 - /* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */ - bl mpmm_errata_disable -#endif workaround_reset_end cortex_a510, ERRATUM(2250311) check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0) @@ -209,6 +195,15 @@ endfunc cortex_a510_core_pwr_dwn cpu_reset_func_start cortex_a510 /* Disable speculative loads */ msr SSBS, xzr + /* skip enabling MPMM if this erratum is present */ +#if ERRATA_A510_2250311 + /* the cpu_rev_var is kept in x14 */ + mov x14, x0 + bl check_erratum_cortex_a510_2250311 + cbz x0, skip_mpmm +#endif + enable_mpmm +skip_mpmm: cpu_reset_func_end cortex_a510 /* --------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S index 6714a53de..ac8019e02 100644 --- a/lib/cpus/aarch64/cortex_a520.S +++ b/lib/cpus/aarch64/cortex_a520.S @@ -58,6 +58,7 @@ endfunc cortex_a520_core_pwr_dwn cpu_reset_func_start cortex_a520 /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_a520 /* --------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index cb24aa116..e8f5a80b3 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -250,6 +250,7 @@ endfunc cortex_a710_core_pwr_dwn cpu_reset_func_start cortex_a710 /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_a710 /* --------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S index e50764d02..d9c0df2d3 100644 --- a/lib/cpus/aarch64/cortex_a715.S +++ b/lib/cpus/aarch64/cortex_a715.S @@ -138,6 +138,7 @@ check_erratum_ls cortex_a715, ERRATUM(3699560), CPU_REV(1, 3) cpu_reset_func_start cortex_a715 /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_a715 /* ---------------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S index 2991f93b9..e639996ca 100644 --- a/lib/cpus/aarch64/cortex_a720.S +++ b/lib/cpus/aarch64/cortex_a720.S @@ -83,6 +83,7 @@ check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2) cpu_reset_func_start cortex_a720 /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_a720 /* ---------------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_a720_ae.S b/lib/cpus/aarch64/cortex_a720_ae.S index c72a29eb8..1d51c44f0 100644 --- a/lib/cpus/aarch64/cortex_a720_ae.S +++ b/lib/cpus/aarch64/cortex_a720_ae.S @@ -32,6 +32,7 @@ check_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0) cpu_reset_func_start cortex_a720_ae /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_a720_ae /* ---------------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S index a8c0db246..682ca45b2 100644 --- a/lib/cpus/aarch64/cortex_a725.S +++ b/lib/cpus/aarch64/cortex_a725.S @@ -32,6 +32,7 @@ check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1) cpu_reset_func_start cortex_a725 /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_a725 /* ---------------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_alto.S b/lib/cpus/aarch64/cortex_alto.S index 97192a6a0..69a630d1f 100644 --- a/lib/cpus/aarch64/cortex_alto.S +++ b/lib/cpus/aarch64/cortex_alto.S @@ -30,6 +30,7 @@ cpu_reset_prologue cortex_alto cpu_reset_func_start cortex_alto /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_alto func cortex_alto_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_arcadia.S b/lib/cpus/aarch64/cortex_arcadia.S index ae8eb91d1..84749b639 100644 --- a/lib/cpus/aarch64/cortex_arcadia.S +++ b/lib/cpus/aarch64/cortex_arcadia.S @@ -26,6 +26,7 @@ cpu_reset_prologue cortex_arcadia cpu_reset_func_start cortex_arcadia /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_arcadia /* ---------------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S index cdf62841a..4cdec3271 100644 --- a/lib/cpus/aarch64/cortex_gelas.S +++ b/lib/cpus/aarch64/cortex_gelas.S @@ -40,6 +40,7 @@ cpu_reset_func_start cortex_gelas /* model bug: not cleared on reset */ sysreg_bit_clear CORTEX_GELAS_CPUPWRCTLR_EL1, \ CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + enable_mpmm cpu_reset_func_end cortex_gelas /* ---------------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index 549beec4f..b11c37ddf 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -195,6 +195,7 @@ endfunc cortex_x2_core_pwr_dwn cpu_reset_func_start cortex_x2 /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_x2 /* --------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index da9e30608..3d52dae30 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -136,6 +136,7 @@ check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 cpu_reset_func_start cortex_x3 /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_x3 /* ---------------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S index 53461c61f..c06798154 100644 --- a/lib/cpus/aarch64/cortex_x4.S +++ b/lib/cpus/aarch64/cortex_x4.S @@ -130,6 +130,7 @@ check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3) cpu_reset_func_start cortex_x4 /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_x4 /* ---------------------------------------------------- diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S index 7dec3752e..093d91d3a 100644 --- a/lib/cpus/aarch64/cortex_x925.S +++ b/lib/cpus/aarch64/cortex_x925.S @@ -63,6 +63,7 @@ check_erratum_chosen cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 cpu_reset_func_start cortex_x925 /* Disable speculative loads */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end cortex_x925 /* ---------------------------------------------------- diff --git a/lib/cpus/aarch64/nevis.S b/lib/cpus/aarch64/nevis.S index 0d04e65ec..b2aa26e28 100644 --- a/lib/cpus/aarch64/nevis.S +++ b/lib/cpus/aarch64/nevis.S @@ -29,6 +29,7 @@ cpu_reset_func_start nevis * ---------------------------------------------------- */ msr SSBS, xzr + enable_mpmm cpu_reset_func_end nevis func nevis_core_pwr_dwn diff --git a/lib/cpus/aarch64/travis.S b/lib/cpus/aarch64/travis.S index 0a95e8009..d53e46f9e 100644 --- a/lib/cpus/aarch64/travis.S +++ b/lib/cpus/aarch64/travis.S @@ -40,6 +40,7 @@ cpu_reset_func_start travis /* model bug: not cleared on reset */ sysreg_bit_clear TRAVIS_IMP_CPUPWRCTLR_EL1, \ TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT + enable_mpmm cpu_reset_func_end travis func travis_core_pwr_dwn diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c index cb9a0f26e..a7898eff0 100644 --- a/lib/extensions/amu/aarch64/amu.c +++ b/lib/extensions/amu/aarch64/amu.c @@ -25,10 +25,6 @@ # include #endif -#if ENABLE_MPMM -# include -#endif - struct amu_ctx { uint64_t group0_cnts[AMU_GROUP0_MAX_COUNTERS]; #if ENABLE_AMU_AUXILIARY_COUNTERS @@ -258,10 +254,6 @@ void amu_init_el3(void) write_amcr_el0_cg1rz(0U); #endif } - -#if ENABLE_MPMM - mpmm_enable(); -#endif } void amu_init_el2_unused(void) diff --git a/lib/fconf/fconf.mk b/lib/fconf/fconf.mk index ff781aa4b..311bee4e8 100644 --- a/lib/fconf/fconf.mk +++ b/lib/fconf/fconf.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2019-2021, Arm Limited. All rights reserved. +# Copyright (c) 2019-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -14,6 +14,3 @@ FCONF_DYN_SOURCES += ${FDT_WRAPPERS_SOURCES} FCONF_AMU_SOURCES := lib/fconf/fconf_amu_getter.c FCONF_AMU_SOURCES += ${FDT_WRAPPERS_SOURCES} - -FCONF_MPMM_SOURCES := lib/fconf/fconf_mpmm_getter.c -FCONF_MPMM_SOURCES += ${FDT_WRAPPERS_SOURCES} diff --git a/lib/fconf/fconf_mpmm_getter.c b/lib/fconf/fconf_mpmm_getter.c deleted file mode 100644 index 02a566d5a..000000000 --- a/lib/fconf/fconf_mpmm_getter.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2021, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include -#include -#include -#include -#include - -#include - -struct fconf_mpmm_config fconf_mpmm_config; -static struct mpmm_topology fconf_mpmm_topology; - -/* - * Within a `cpu` node, determine support for MPMM via the `supports-mpmm` - * property. - * - * Returns `0` on success, or a negative integer representing an error code. - */ -static int fconf_populate_mpmm_cpu(const void *fdt, int off, uintptr_t mpidr) -{ - int ret, len; - - int core_pos; - struct mpmm_core *core; - - core_pos = plat_core_pos_by_mpidr(mpidr); - if (core_pos < 0) { - return -FDT_ERR_BADVALUE; - } - - core = &fconf_mpmm_topology.cores[core_pos]; - - fdt_getprop(fdt, off, "supports-mpmm", &len); - if (len >= 0) { - core->supported = true; - ret = 0; - } else { - core->supported = false; - ret = len; - } - - return ret; -} - -/* - * Populates the global `fconf_mpmm_config` structure based on what's described - * by the hardware configuration device tree blob. - * - * The device tree is expected to provide a `supports-mpmm` property for each - * `cpu` node, like so: - * - * cpu@0 { - * supports-mpmm; - * }; - * - * This property indicates whether the core implements MPMM, as we cannot detect - * support for it dynamically. - */ -static int fconf_populate_mpmm(uintptr_t config) -{ - int ret = fdtw_for_each_cpu( - (const void *)config, fconf_populate_mpmm_cpu); - if (ret == 0) { - fconf_mpmm_config.topology = &fconf_mpmm_topology; - } else { - ERROR("FCONF: failed to configure MPMM: %d\n", ret); - } - - return ret; -} - -FCONF_REGISTER_POPULATOR(HW_CONFIG, mpmm, fconf_populate_mpmm); diff --git a/lib/mpmm/mpmm.c b/lib/mpmm/mpmm.c deleted file mode 100644 index dc61cf62a..000000000 --- a/lib/mpmm/mpmm.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -#include - -#if ENABLE_MPMM_FCONF -# include -# include -#endif - -static uint64_t read_cpuppmcr_el3_mpmmpinctl(void) -{ - return (read_cpuppmcr_el3() >> CPUPPMCR_EL3_MPMMPINCTL_SHIFT) & - CPUPPMCR_EL3_MPMMPINCTL_MASK; -} - -static void write_cpumpmmcr_el3_mpmm_en(uint64_t mpmm_en) -{ - uint64_t value = read_cpumpmmcr_el3(); - - value &= ~(CPUMPMMCR_EL3_MPMM_EN_MASK << CPUMPMMCR_EL3_MPMM_EN_SHIFT); - value |= (mpmm_en & CPUMPMMCR_EL3_MPMM_EN_MASK) << - CPUMPMMCR_EL3_MPMM_EN_SHIFT; - - write_cpumpmmcr_el3(value); -} - -static bool mpmm_supported(void) -{ - bool supported = false; - const struct mpmm_topology *topology; - -#if ENABLE_MPMM_FCONF - topology = FCONF_GET_PROPERTY(mpmm, config, topology); -#else - topology = plat_mpmm_topology(); -#endif /* ENABLE_MPMM_FCONF */ - - /* - * For the current core firstly try to find out if the platform - * configuration has claimed support for MPMM, then make sure that MPMM - * is controllable through the system registers. - */ - - if (topology != NULL) { - unsigned int core_pos = plat_my_core_pos(); - - supported = topology->cores[core_pos].supported && - (read_cpuppmcr_el3_mpmmpinctl() == 0U); - } else { - ERROR("MPMM: failed to generate MPMM topology\n"); - } - - return supported; -} - -/* Defaults to false */ -static bool mpmm_disable_for_errata; - -void mpmm_enable(void) -{ - if (mpmm_supported()) { - if (mpmm_disable_for_errata) { - WARN("MPMM: disabled by errata workaround\n"); - return; - } - write_cpumpmmcr_el3_mpmm_en(1U); - } -} - -/* - * This function is called from assembly code very early in BL31 so it must be - * small and simple. - */ -void mpmm_errata_disable(void) -{ - mpmm_disable_for_errata = true; -} diff --git a/lib/mpmm/mpmm.mk b/lib/mpmm/mpmm.mk deleted file mode 100644 index 826f9253b..000000000 --- a/lib/mpmm/mpmm.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright (c) 2021, Arm Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include lib/extensions/amu/amu.mk -include lib/fconf/fconf.mk - -ifneq (${ENABLE_MPMM},0) - ifneq ($(ARCH),aarch64) - $(error MPMM support (`ENABLE_MPMM`) can only be enabled in AArch64 images (`ARCH`)) - endif - - ifeq (${ENABLE_AMU_AUXILIARY_COUNTERS},0) # For MPMM gear AMU counters - $(error MPMM support (`ENABLE_MPM`) requires auxiliary AMU counter support (`ENABLE_AMU_AUXILIARY_COUNTERS`)) - endif -endif - -MPMM_SOURCES := lib/mpmm/mpmm.c -MPMM_SOURCES += ${AMU_SOURCES} - -ifneq (${ENABLE_MPMM_FCONF},0) - ifeq (${ENABLE_MPMM},0) - $(error MPMM FCONF support (`ENABLE_MPMM_FCONF`) requires MPMM support (`ENABLE_MPMM`)) - endif - - MPMM_SOURCES += ${FCONF_MPMM_SOURCES} -endif diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index d5149333b..ec2aa1bfb 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -88,9 +88,6 @@ ENABLE_MPMM := 0 # Enable support for powerdown abandons FEAT_PABANDON := 0 -# Enable MPMM configuration via FCONF. -ENABLE_MPMM_FCONF := 0 - # Flag to Enable Position Independant support (PIE) ENABLE_PIE := 0 diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index 1e12a127a..49f9eea27 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -35,7 +35,6 @@ ENABLE_FEAT_AMU := 1 ENABLE_AMU_FCONF := 1 ENABLE_AMU_AUXILIARY_COUNTERS := 1 ENABLE_MPMM := 1 -ENABLE_MPMM_FCONF := 1 ENABLE_FEAT_MTE2 := 2 ENABLE_SPE_FOR_NS := 3 ENABLE_FEAT_TCR2 := 3