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Merge changes I134f125f,Ia4bf45bf into integration

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* changes:
  refactor(sgi): rename RD-Edmunds to RD-V2
  refactor(cpu): use the updated IP name for Demeter CPU
This commit is contained in:
Manish V Badarkhe 2022-10-04 10:45:50 +02:00 • committed by TrustedFirmware Code Review
commit 252b2bd8a3
7 changed files with 44 additions and 44 deletions
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2
docs/security_advisories/security-advisory-tfv-9.rst
View file

@ -85,7 +85,7 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
+----------------------+
| Neoverse-V1 |
+----------------------+
| Neoverse-Demeter |
| Neoverse-V2 |
+----------------------+
| Neoverse-Poseidon |
+----------------------+

18
include/lib/cpus/aarch64/neoverse_demeter.h → include/lib/cpus/aarch64/neoverse_v2.h
View file

@ -4,23 +4,23 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef NEOVERSE_DEMETER_H
#define NEOVERSE_DEMETER_H
#ifndef NEOVERSE_V2_H
#define NEOVERSE_V2_H
#define NEOVERSE_DEMETER_MIDR U(0x410FD4F0)
#define NEOVERSE_V2_MIDR U(0x410FD4F0)
/* Neoverse Demeter loop count for CVE-2022-23960 mitigation */
#define NEOVERSE_DEMETER_BHB_LOOP_COUNT U(132)
/* Neoverse V2 loop count for CVE-2022-23960 mitigation */
#define NEOVERSE_V2_BHB_LOOP_COUNT U(132)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define NEOVERSE_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4
#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* NEOVERSE_DEMETER_H */
#endif /* NEOVERSE_V2_H */

54
lib/cpus/aarch64/neoverse_demeter.S → lib/cpus/aarch64/neoverse_v2.S
View file

@ -7,40 +7,40 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <neoverse_demeter.h>
#include <neoverse_v2.h>
#include <cpu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse Demeter must be compiled with HW_ASSISTED_COHERENCY enabled"
#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_DEMETER_BHB_LOOP_COUNT, neoverse_demeter
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
#endif /* WORKAROUND_CVE_2022_23960 */
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func neoverse_demeter_core_pwr_dwn
func neoverse_v2_core_pwr_dwn
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
mrs x0, NEOVERSE_DEMETER_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_DEMETER_CPUPWRCTLR_EL1, x0
mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
isb
ret
endfunc neoverse_demeter_core_pwr_dwn
endfunc neoverse_v2_core_pwr_dwn
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
@ -51,27 +51,27 @@ func check_errata_cve_2022_23960
ret
endfunc check_errata_cve_2022_23960
func neoverse_demeter_reset_func
func neoverse_v2_reset_func
/* Disable speculative loads */
msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Neoverse Demeter vectors are overridden to apply
* The Neoverse V2 vectors are overridden to apply
* errata mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_neoverse_demeter
adr x0, wa_cve_vbar_neoverse_v2
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb
ret
endfunc neoverse_demeter_reset_func
endfunc neoverse_v2_reset_func
#if REPORT_ERRATA
/*
* Errata printing function for Neoverse Demeter. Must follow AAPCS.
* Errata printing function for Neoverse V2. Must follow AAPCS.
*/
func neoverse_demeter_errata_report
func neoverse_v2_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
@ -81,15 +81,15 @@ func neoverse_demeter_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2022_23960, neoverse_demeter, cve_2022_23960
report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc neoverse_demeter_errata_report
endfunc neoverse_v2_errata_report
#endif
/* ---------------------------------------------
* This function provides Neoverse Demeter-
* This function provides Neoverse V2-
* specific register information for crash
* reporting. It needs to return with x6
* pointing to a list of register names in ascii
@ -97,16 +97,16 @@ endfunc neoverse_demeter_errata_report
* reported.
* ---------------------------------------------
*/
.section .rodata.neoverse_demeter_regs, "aS"
neoverse_demeter_regs: /* The ascii list of register names to be reported */
.section .rodata.neoverse_v2_regs, "aS"
neoverse_v2_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func neoverse_demeter_cpu_reg_dump
adr x6, neoverse_demeter_regs
mrs x8, NEOVERSE_DEMETER_CPUECTLR_EL1
func neoverse_v2_cpu_reg_dump
adr x6, neoverse_v2_regs
mrs x8, NEOVERSE_V2_CPUECTLR_EL1
ret
endfunc neoverse_demeter_cpu_reg_dump
endfunc neoverse_v2_cpu_reg_dump
declare_cpu_ops neoverse_demeter, NEOVERSE_DEMETER_MIDR, \
neoverse_demeter_reset_func, \
neoverse_demeter_core_pwr_dwn
declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
neoverse_v2_reset_func, \
neoverse_v2_core_pwr_dwn

2
plat/arm/board/fvp/platform.mk
View file

@ -132,7 +132,7 @@ else
lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/neoverse_demeter.S \
lib/cpus/aarch64/neoverse_v2.S \
lib/cpus/aarch64/cortex_a78_ae.S \
lib/cpus/aarch64/cortex_a510.S \
lib/cpus/aarch64/cortex_a710.S \

2
plat/arm/board/rdn2/platform.mk
View file

@ -34,7 +34,7 @@ RDN2_BASE = plat/arm/board/rdn2
PLAT_INCLUDES += -I${RDN2_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_demeter.S
lib/cpus/aarch64/neoverse_v2.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c

8
plat/arm/css/sgi/include/sgi_variant.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -23,9 +23,9 @@
/* SID Version values for RD-N2 variants */
#define RD_N2_CFG1_SID_VER_PART_NUM 0x07B6
/* SID Version values for RD-Edmunds */
#define RD_EDMUNDS_SID_VER_PART_NUM 0x07F2
#define RD_EDMUNDS_CONFIG_ID 0x1
/* SID Version values for RD-V2 */
#define RD_V2_SID_VER_PART_NUM 0x07F2
#define RD_V2_CONFIG_ID 0x1
/* Structure containing SGI platform variant information */
typedef struct sgi_platform_info {

2
plat/arm/css/sgi/sgi_bl31_setup.c
View file

@ -79,7 +79,7 @@ scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_EDMUNDS_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_V2_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) {
if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
panic();