mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 01:24:27 +00:00
Merge "feat(ufs): adds timeout and error handling" into integration
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
2519ee5ffe
2 changed files with 191 additions and 24 deletions
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@ -30,9 +30,138 @@
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static ufs_params_t ufs_params;
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static int nutrs; /* Number of UTP Transfer Request Slots */
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/*
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* ufs_uic_error_handler - UIC error interrupts handler
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* @ignore_linereset: set to ignore PA_LAYER_GEN_ERR (UIC error)
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*
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* Returns
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* 0 - ignore error
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* -EIO - fatal error, needs re-init
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* -EAGAIN - non-fatal error, retries are sufficient
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*/
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static int ufs_uic_error_handler(bool ignore_linereset)
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{
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uint32_t data;
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int result = 0;
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data = mmio_read_32(ufs_params.reg_base + UECPA);
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if (data & UFS_UIC_PA_ERROR_MASK) {
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if (data & PA_LAYER_GEN_ERR) {
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if (!ignore_linereset) {
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return -EIO;
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}
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} else {
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result = -EAGAIN;
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}
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}
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data = mmio_read_32(ufs_params.reg_base + UECDL);
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if (data & UFS_UIC_DL_ERROR_MASK) {
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if (data & PA_INIT_ERR) {
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return -EIO;
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}
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result = -EAGAIN;
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}
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/* NL/TL/DME error requires retries */
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data = mmio_read_32(ufs_params.reg_base + UECN);
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if (data & UFS_UIC_NL_ERROR_MASK) {
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result = -EAGAIN;
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}
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data = mmio_read_32(ufs_params.reg_base + UECT);
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if (data & UFS_UIC_TL_ERROR_MASK) {
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result = -EAGAIN;
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}
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data = mmio_read_32(ufs_params.reg_base + UECDME);
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if (data & UFS_UIC_DME_ERROR_MASK) {
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result = -EAGAIN;
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}
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return result;
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}
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/*
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* ufs_error_handler - error interrupts handler
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* @status: interrupt status
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* @ignore_linereset: set to ignore PA_LAYER_GEN_ERR (UIC error)
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*
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* Returns
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* 0 - ignore error
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* -EIO - fatal error, needs re-init
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* -EAGAIN - non-fatal error, retries are sufficient
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*/
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static int ufs_error_handler(uint32_t status, bool ignore_linereset)
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{
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int result;
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if (status & UFS_INT_UE) {
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result = ufs_uic_error_handler(ignore_linereset);
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if (result != 0) {
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return result;
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}
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}
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/* Return I/O error on fatal error, it is upto the caller to re-init UFS */
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if (status & UFS_INT_FATAL) {
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return -EIO;
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}
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/* retry for non-fatal errors */
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return -EAGAIN;
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}
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/*
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* ufs_wait_for_int_status - wait for expected interrupt status
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* @expected: expected interrupt status bit
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* @timeout_ms: timeout in milliseconds to poll for
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* @ignore_linereset: set to ignore PA_LAYER_GEN_ERR (UIC error)
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*
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* Returns
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* 0 - received expected interrupt and cleared it
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* -EIO - fatal error, needs re-init
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* -EAGAIN - non-fatal error, caller can retry
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* -ETIMEDOUT - timed out waiting for interrupt status
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*/
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static int ufs_wait_for_int_status(const uint32_t expected_status,
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unsigned int timeout_ms,
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bool ignore_linereset)
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{
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uint32_t interrupt_status, interrupts_enabled;
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int result = 0;
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interrupts_enabled = mmio_read_32(ufs_params.reg_base + IE);
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do {
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interrupt_status = mmio_read_32(ufs_params.reg_base + IS) & interrupts_enabled;
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if (interrupt_status & UFS_INT_ERR) {
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mmio_write_32(ufs_params.reg_base + IS, interrupt_status & UFS_INT_ERR);
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result = ufs_error_handler(interrupt_status, ignore_linereset);
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if (result != 0) {
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return result;
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}
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}
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if (interrupt_status & expected_status) {
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break;
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}
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mdelay(1);
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} while (timeout_ms-- > 0);
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if (!(interrupt_status & expected_status)) {
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return -ETIMEDOUT;
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}
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mmio_write_32(ufs_params.reg_base + IS, expected_status);
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return result;
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}
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int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd)
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{
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unsigned int data;
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int result;
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if (base == 0 || cmd == NULL)
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return -EINVAL;
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@ -46,10 +175,12 @@ int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd)
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mmio_write_32(base + UCMDARG3, cmd->arg3);
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mmio_write_32(base + UICCMD, cmd->op);
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do {
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data = mmio_read_32(base + IS);
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} while ((data & UFS_INT_UCCS) == 0);
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mmio_write_32(base + IS, UFS_INT_UCCS);
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result = ufs_wait_for_int_status(UFS_INT_UCCS, UIC_CMD_TIMEOUT_MS,
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cmd->op == DME_SET);
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if (result != 0) {
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return result;
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}
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return mmio_read_32(base + UCMDARG2) & CONFIG_RESULT_CODE_MASK;
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}
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@ -83,9 +214,10 @@ int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val)
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result = ufshc_send_uic_cmd(base, &cmd);
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if (result == 0)
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break;
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data = mmio_read_32(base + IS);
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if (data & UFS_INT_UE)
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return -EINVAL;
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/* -EIO requires UFS re-init */
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if (result == -EIO) {
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return result;
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}
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}
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if (retries >= UFS_UIC_COMMAND_RETRIES)
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return -EIO;
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@ -97,7 +229,6 @@ int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val)
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int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val)
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{
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uintptr_t base;
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unsigned int data;
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int result, retries;
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uic_cmd_t cmd;
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@ -113,9 +244,10 @@ int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val)
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result = ufshc_send_uic_cmd(base, &cmd);
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if (result == 0)
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break;
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data = mmio_read_32(base + IS);
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if (data & UFS_INT_UE)
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return -EINVAL;
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/* -EIO requires UFS re-init */
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if (result == -EIO) {
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return result;
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}
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}
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if (retries >= UFS_UIC_COMMAND_RETRIES)
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return -EIO;
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@ -193,9 +325,10 @@ static int ufshc_reset(uintptr_t base)
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return -EIO;
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}
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/* Enable Interrupts */
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data = UFS_INT_UCCS | UFS_INT_ULSS | UFS_INT_UE | UFS_INT_UTPES |
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UFS_INT_DFES | UFS_INT_HCFES | UFS_INT_SBFES;
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/* Enable UIC Interrupts alone. We can ignore other interrupts until
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* link is up as there might be spurious error interrupts during link-up
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*/
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data = UFS_INT_UCCS | UFS_INT_UHES | UFS_INT_UHXS | UFS_INT_UPMS;
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mmio_write_32(base + IE, data);
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return 0;
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@ -229,6 +362,13 @@ static int ufshc_link_startup(uintptr_t base)
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data = mmio_read_32(base + IS);
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if (data & UFS_INT_ULSS)
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mmio_write_32(base + IS, UFS_INT_ULSS);
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/* clear UE set due to line-reset */
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if (data & UFS_INT_UE) {
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mmio_write_32(base + IS, UFS_INT_UE);
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}
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/* clearing line-reset, UECPA is cleared on read */
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mmio_read_32(base + UECPA);
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return 0;
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}
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return -EIO;
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@ -472,21 +612,22 @@ static void ufs_send_request(int task_tag)
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mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot);
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}
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static int ufs_check_resp(utp_utrd_t *utrd, int trans_type)
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static int ufs_check_resp(utp_utrd_t *utrd, int trans_type, unsigned int timeout_ms)
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{
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utrd_header_t *hd;
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resp_upiu_t *resp;
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sense_data_t *sense;
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unsigned int data;
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int slot;
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int slot, result;
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hd = (utrd_header_t *)utrd->header;
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resp = (resp_upiu_t *)utrd->resp_upiu;
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do {
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data = mmio_read_32(ufs_params.reg_base + IS);
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if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0)
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return -EIO;
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} while ((data & UFS_INT_UTRCS) == 0);
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result = ufs_wait_for_int_status(UFS_INT_UTRCS, timeout_ms, false);
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if (result != 0) {
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return result;
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}
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slot = utrd->task_tag - 1;
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data = mmio_read_32(ufs_params.reg_base + UTRLDBR);
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@ -510,6 +651,7 @@ static int ufs_check_resp(utp_utrd_t *utrd, int trans_type)
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(void)resp;
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(void)slot;
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(void)data;
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return 0;
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}
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@ -523,7 +665,7 @@ static void ufs_send_cmd(utp_utrd_t *utrd, uint8_t cmd_op, uint8_t lun, int lba,
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result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length);
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assert(result == 0);
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ufs_send_request(utrd->task_tag);
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result = ufs_check_resp(utrd, RESPONSE_UPIU);
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result = ufs_check_resp(utrd, RESPONSE_UPIU, CMD_TIMEOUT_MS);
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if (result == 0 || result == -EIO) {
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break;
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}
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@ -574,7 +716,7 @@ static void ufs_verify_init(void)
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get_utrd(&utrd);
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ufs_prepare_nop_out(&utrd);
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ufs_send_request(utrd.task_tag);
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result = ufs_check_resp(&utrd, NOP_IN_UPIU);
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result = ufs_check_resp(&utrd, NOP_IN_UPIU, NOP_OUT_TIMEOUT_MS);
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assert(result == 0);
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(void)result;
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}
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@ -607,7 +749,7 @@ static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel,
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get_utrd(&utrd);
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ufs_prepare_query(&utrd, op, idn, index, sel, buf, size);
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ufs_send_request(utrd.task_tag);
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result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU);
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result = ufs_check_resp(&utrd, QUERY_RESPONSE_UPIU, QUERY_REQ_TIMEOUT_MS);
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assert(result == 0);
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resp = (query_resp_upiu_t *)utrd.resp_upiu;
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#ifdef UFS_RESP_DEBUG
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@ -895,6 +1037,11 @@ int ufs_init(const ufs_ops_t *ops, ufs_params_t *params)
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result = ufshc_link_startup(ufs_params.reg_base);
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assert(result == 0);
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/* enable all interrupts */
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data = UFS_INT_UCCS | UFS_INT_UHES | UFS_INT_UHXS | UFS_INT_UPMS;
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data |= UFS_INT_UTRCS | UFS_INT_ERR;
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mmio_write_32(ufs_params.reg_base + IE, data);
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ufs_enum();
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ufs_get_device_info(&card);
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@ -57,6 +57,21 @@
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/* UTP Transfer Request Completion Status */
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#define UFS_INT_UTRCS (1 << 0)
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#define UFS_INT_FATAL (UFS_INT_DFES |\
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UFS_INT_HCFES |\
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UFS_INT_SBFES)
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#define UFS_INT_ERR (UFS_INT_FATAL |\
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UFS_INT_UE)
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#define UFS_UIC_PA_ERROR_MASK 0x8000001F
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#define UFS_UIC_DL_ERROR_MASK 0x8000FFFF
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#define UFS_UIC_NL_ERROR_MASK 0x80000007
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#define UFS_UIC_TL_ERROR_MASK 0x8000007F
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#define UFS_UIC_DME_ERROR_MASK 0x80000001
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#define PA_INIT_ERR (1 << 13)
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#define PA_LAYER_GEN_ERR (1 << 4)
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/* Host Controller Status */
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#define HCS 0x30
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#define HCS_UPMCRS_MASK (7 << 8)
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@ -275,6 +290,11 @@
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#define FDEVICEINIT_TIMEOUT_MS 1500
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#define UIC_CMD_TIMEOUT_MS 500
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#define QUERY_REQ_TIMEOUT_MS 1500
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#define NOP_OUT_TIMEOUT_MS 50
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#define CMD_TIMEOUT_MS 5000
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/**
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* ufs_dev_desc - ufs device details from the device descriptor
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* @wmanufacturerid: card details
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