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feat(mediatek): configure DEV_IRQ as G1S interrupt

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In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK GIC driver to configure the interrupt properly.

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Change-Id: Id909a42b535088c6d0dcaf803d3f2faf312ae846
This commit is contained in:
Gavin Liu 2024-06-17 17:11:52 +08:00 • committed by Gavin Liu
parent 620a3ddb01
commit 240a1ecd18
5 changed files with 26 additions and 6 deletions
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8
plat/mediatek/drivers/gic600/mt_gic_v3.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
* Copyright (c) 2020-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,6 +27,10 @@ static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
/* we save and restore the GICv3 context on system suspend */
gicv3_dist_ctx_t dist_ctx;
static const interrupt_prop_t mtk_interrupt_props[] = {
PLAT_MTK_G1S_IRQ_PROPS(INTR_GROUP1S)
};
static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
{
return plat_core_pos_by_mpidr(mpidr);
@ -35,6 +39,8 @@ static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
gicv3_driver_data_t mt_gicv3_data = {
.gicd_base = MT_GIC_BASE,
.gicr_base = MT_GIC_RDIST_BASE,
.interrupt_props = mtk_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(mtk_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,
.rdistif_base_addrs = rdistif_base_addrs,
.mpidr_to_core_pos = mt_mpidr_to_core_pos,

6
plat/mediatek/mt8186/include/platform_def.h
View file

@ -1,6 +1,6 @@
/*
* Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
* Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -83,6 +83,8 @@
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
#define PLAT_MTK_G1S_IRQ_PROPS(grp)
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM (11)
#define CIRQ_IRQ_NUM (326)

7
plat/mediatek/mt8188/include/platform_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -96,6 +96,11 @@
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE (MT_GIC_BASE)
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
#define DEV_IRQ_ID 580
#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL)
/*******************************************************************************
* CIRQ related constants

4
plat/mediatek/mt8192/include/platform_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -82,6 +82,8 @@
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
#define PLAT_MTK_G1S_IRQ_PROPS(grp)
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM 14
#define CIRQ_IRQ_NUM 439

7
plat/mediatek/mt8195/include/platform_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -95,6 +95,11 @@
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
#define DEV_IRQ_ID 580
#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL)
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM 23