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refactor(cpufeat): align FEAT_SB to new feature handling

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FEAT_SB introduces a new speculation barrier instruction, that is more
lightweight than a "dsb; isb" combination. We use that in a hot path,
so cannot afford and don't want a runtime detection mechanism.
Nevertheless align the implementation of the feature detection part
with the other features, but renaming the detection function, and
updating the FEAT_DETECTION code. Also update the documentation.

Change-Id: I2b86dfd1ad259c3bb99ab5186e2911ace454b54c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2022-11-17 16:42:09 +00:00
parent 387b8801f9
commit 240770989f
4 changed files with 9 additions and 21 deletions
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2
Makefile
View file

@ -1090,6 +1090,7 @@ $(eval $(call assert_booleans,\
ENABLE_AMU_FCONF \
AMU_RESTRICT_COUNTERS \
ENABLE_ASSERTIONS \
ENABLE_FEAT_SB \
ENABLE_PIE \
ENABLE_PMF \
ENABLE_PSCI_STAT \
@ -1174,7 +1175,6 @@ $(eval $(call assert_numerics,\
ENABLE_FEAT_PAN \
ENABLE_FEAT_RNG \
ENABLE_FEAT_RNG_TRAP \
ENABLE_FEAT_SB \
ENABLE_FEAT_SEL2 \
ENABLE_FEAT_TCR2 \
ENABLE_FEAT_VHE \

12
common/feat_detect.c
View file

@ -60,16 +60,6 @@ check_feature(int state, unsigned long field, const char *feat_name,
}
}
/******************************************
* Feature : FEAT_SB (Speculation Barrier)
*****************************************/
static void read_feat_sb(void)
{
#if (ENABLE_FEAT_SB == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_0_feat_sb_present(), "SB");
#endif
}
/******************************************************
* Feature : FEAT_CSV2_2 (Cache Speculation Variant 2)
*****************************************************/
@ -256,7 +246,7 @@ void detect_arch_features(void)
tainted = false;
/* v8.0 features */
read_feat_sb();
check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", 1, 1);
read_feat_csv2_2();
/* v8.1 features */

11
docs/getting_started/build-options.rst
View file

@ -327,12 +327,11 @@ Common build options
Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from
Armv8.5 onwards.
- ``ENABLE_FEAT_SB``: Numeric value to enable the ``FEAT_SB`` (Speculation
Barrier) extension allowing access to ``sb`` instruction. ``FEAT_SB`` is an
optional feature and defaults to ``0`` for pre-Armv8.5 CPUs but are mandatory
for Armv8.5 or later CPUs. This flag can take values 0 to 2, to align with
``FEATURE_DETECTION`` mechanism. It is enabled from v8.5 and upwards and if
needed could be overidden from platforms explicitly. Default value is ``0``.
- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB``
(Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and
defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or
later CPUs. It is enabled from v8.5 and upwards and if needed can be
overidden from platforms explicitly.
- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2)
extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4.

5
include/arch/aarch64/arch_features.h
View file

@ -256,10 +256,9 @@ static inline unsigned int get_armv9_2_feat_rme_support(void)
/*********************************************************************************
* Function to identify the presence of FEAT_SB (Speculation Barrier Instruction)
********************************************************************************/
static inline bool is_armv8_0_feat_sb_present(void)
static inline unsigned int read_feat_sb_id_field(void)
{
return (((read_id_aa64isar1_el1() >> ID_AA64ISAR1_SB_SHIFT) &
ID_AA64ISAR1_SB_MASK) == ID_AA64ISAR1_SB_SUPPORTED);
return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB);
}
/*********************************************************************************