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fix(stm32mp2): correct early/crash console init

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The previous code used 64-bit registers as the target and source for
load and store operations on 32-bit hardware registers. In certain
cases (e.g., when using USART1 as the debug console), this could result
in deadlocks where the A35 gets stuck in a permanent loop due to test
conditions that are never fulfilled.

To resolve this issue, 32-bit registers are now used for these
operations.

Change-Id: Id2c03a1df26738fe815079da042cc2dd989f4f8e
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>
This commit is contained in:
Boerge Struempfel 2025-01-27 20:31:37 +01:00
parent bba792b165
commit 23647bd52c
No known key found for this signature in database
GPG key ID: 9557AEA0BDE5D28A
1 changed files with 10 additions and 10 deletions
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20
plat/st/stm32mp2/aarch64/stm32mp2_helper.S
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@ -90,19 +90,19 @@ endfunc plat_my_core_pos
func plat_crash_console_init
/* Reset UART peripheral */
mov_imm x1, (RCC_BASE + DEBUG_UART_RST_REG)
ldr x2, =DEBUG_UART_RST_BIT
ldr x0, [x1]
orr x0, x0, x2
str x0, [x1]
ldr w2, =DEBUG_UART_RST_BIT
ldr w0, [x1]
orr w0, w0, w2
str w0, [x1]
1:
ldr x0, [x1]
tst x0, #DEBUG_UART_RST_BIT
ldr w0, [x1]
tst w0, #DEBUG_UART_RST_BIT
beq 1b
bic x0, x0, #DEBUG_UART_RST_BIT
str x0, [x1]
bic w0, w0, #DEBUG_UART_RST_BIT
str w0, [x1]
2:
ldr x0, [x1]
tst x0, #DEBUG_UART_RST_BIT
ldr w0, [x1]
tst w0, #DEBUG_UART_RST_BIT
bne 2b
/* Enable GPIOs for UART TX */
mov_imm x1, (RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)