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fix(drtm): do cache maintenance before launching DLME

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According to the specifications, the DLME launch should occur with
the cache disabled. Initially, the cache was enabled to enhance
performance. However, to comply with the PSCI specification, we
decided to disable it before launching the DLME.

Also, ensure that full DLME region is invalidated.

Change-Id: Idf619afb7e4a34ebe213bd3b559105ade993f3ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
This commit is contained in:
Manish V Badarkhe 2024-08-30 10:13:43 +01:00 • committed by Manish V Badarkhe
parent cb008a1240
commit 23378ae0bd
1 changed files with 7 additions and 3 deletions
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10
services/std_svc/drtm/drtm_main.c
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@ -463,7 +463,7 @@ static enum drtm_retc drtm_dl_check_args(uint64_t x1,
* is required to avoid / defend against racing with cache evictions
*/
va_mapping_size = ALIGNED_UP((dlme_end - dlme_start), DRTM_PAGE_SIZE);
rc = mmap_add_dynamic_region_alloc_va(dlme_img_start, &va_mapping, va_mapping_size,
rc = mmap_add_dynamic_region_alloc_va(dlme_start, &va_mapping, va_mapping_size,
MT_MEMORY | MT_NS | MT_RO |
MT_SHAREABILITY_ISH);
if (rc != 0) {
@ -512,10 +512,10 @@ static void drtm_dl_reset_dlme_el_state(enum drtm_dlme_el dlme_el)
sctlr &= ~(/* Disable DLME's EL MMU, since the existing page-tables are untrusted. */
SCTLR_M_BIT
| SCTLR_EE_BIT /* Little-endian data accesses. */
| SCTLR_C_BIT /* disable data caching */
| SCTLR_I_BIT /* disable instruction caching */
);
sctlr |= SCTLR_C_BIT | SCTLR_I_BIT; /* Allow instruction and data caching. */
switch (dlme_el) {
case DLME_AT_EL1:
write_sctlr_el1(sctlr);
@ -655,6 +655,10 @@ static uint64_t drtm_dynamic_launch(uint64_t x1, void *handle)
drtm_dl_reset_dlme_el_state(dlme_el);
drtm_dl_reset_dlme_context(dlme_el);
/*
* Setting the Generic Timer frequency is required before launching
* DLME and is already done for running CPU during PSCI setup.
*/
drtm_dl_prepare_eret_to_dlme(&args, dlme_el);
/*