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Workaround for Neoverse N1 erratum 1165347

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Neoverse N1 erratum 1165347 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
This commit is contained in:
lauwal01 2019-06-24 11:32:40 -05:00
parent e34606f2e4
commit 2017ab241c
4 changed files with 47 additions and 0 deletions
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3
docs/design/cpu-specific-build-macros.rst
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@ -234,6 +234,9 @@ For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.