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refactor(stm32mp1): add helpers for IO compensation cells
Add enable_io_comp_cell and disable_io_comp_cell local helpers to enable or disable an IO compensation cell. Change-Id: I65295298a7ece572ae939e2db93d10b188de0f9e Signed-off-by: Yann Gautier <yann.gautier@st.com>
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c7a66e720a
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3 changed files with 57 additions and 36 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -308,6 +308,8 @@ skip_console_init:
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print_reset_reason();
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stm32mp1_syscfg_enable_io_compensation_finish();
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#if !STM32MP_USE_STM32IMAGE
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fconf_populate("TB_FW", STM32MP_DTB_BASE);
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#endif /* !STM32MP_USE_STM32IMAGE */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -18,7 +18,8 @@ void stm32mp1_gic_pcpu_init(void);
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void stm32mp1_gic_init(void);
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void stm32mp1_syscfg_init(void);
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void stm32mp1_syscfg_enable_io_compensation(void);
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void stm32mp1_syscfg_enable_io_compensation_start(void);
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void stm32mp1_syscfg_enable_io_compensation_finish(void);
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void stm32mp1_syscfg_disable_io_compensation(void);
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void stm32mp1_deconfigure_uart_pins(void);
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@ -25,6 +25,9 @@
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#define SYSCFG_CMPENSETR 0x24U
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#define SYSCFG_CMPENCLRR 0x28U
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#define CMPCR_CMPENSETR_OFFSET 0x4U
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#define CMPCR_CMPENCLRR_OFFSET 0x8U
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/*
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* SYSCFG_BOOTR Register
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*/
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@ -62,6 +65,45 @@
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*/
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#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
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static void enable_io_comp_cell_finish(uintptr_t cmpcr_off)
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{
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uint64_t start;
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start = timeout_init_us(SYSCFG_CMPCR_READY_TIMEOUT_US);
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while ((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) {
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if (timeout_elapsed(start)) {
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/* Failure on IO compensation enable is not a issue: warn only. */
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WARN("IO compensation cell not ready\n");
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break;
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}
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}
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mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_SW_CTRL);
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}
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static void disable_io_comp_cell(uintptr_t cmpcr_off)
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{
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uint32_t value;
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if (((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) ||
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((mmio_read_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENSETR_OFFSET) &
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SYSCFG_CMPENSETR_MPU_EN) == 0U)) {
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return;
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}
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value = mmio_read_32(SYSCFG_BASE + cmpcr_off) >> SYSCFG_CMPCR_ANSRC_SHIFT;
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mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
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value <<= SYSCFG_CMPCR_RANSRC_SHIFT;
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value |= mmio_read_32(SYSCFG_BASE + cmpcr_off);
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mmio_write_32(SYSCFG_BASE + cmpcr_off, value | SYSCFG_CMPCR_SW_CTRL);
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mmio_setbits_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN);
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}
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void stm32mp1_syscfg_init(void)
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{
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uint32_t bootr;
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@ -127,13 +169,11 @@ void stm32mp1_syscfg_init(void)
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}
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}
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stm32mp1_syscfg_enable_io_compensation();
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stm32mp1_syscfg_enable_io_compensation_start();
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}
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void stm32mp1_syscfg_enable_io_compensation(void)
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void stm32mp1_syscfg_enable_io_compensation_start(void)
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{
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uint64_t start;
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/*
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* Activate automatic I/O compensation.
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* Warning: need to ensure CSI enabled and ready in clock driver.
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@ -141,29 +181,18 @@ void stm32mp1_syscfg_enable_io_compensation(void)
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*/
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clk_enable(SYSCFG);
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mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
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mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPCR,
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SYSCFG_CMPENSETR_MPU_EN);
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}
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start = timeout_init_us(SYSCFG_CMPCR_READY_TIMEOUT_US);
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while ((mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) &
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SYSCFG_CMPCR_READY) == 0U) {
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if (timeout_elapsed(start)) {
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/*
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* Failure on IO compensation enable is not a issue:
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* warn only.
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*/
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WARN("IO compensation cell not ready\n");
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break;
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}
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}
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mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
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void stm32mp1_syscfg_enable_io_compensation_finish(void)
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{
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enable_io_comp_cell_finish(SYSCFG_CMPCR);
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}
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void stm32mp1_syscfg_disable_io_compensation(void)
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{
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uint32_t value;
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clk_enable(SYSCFG);
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/*
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* Deactivate automatic I/O compensation.
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@ -171,18 +200,7 @@ void stm32mp1_syscfg_disable_io_compensation(void)
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* requested for other usages and always OFF in STANDBY.
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* Disable non-secure SYSCFG clock, we assume non-secure is suspended.
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*/
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value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) >>
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SYSCFG_CMPCR_ANSRC_SHIFT;
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mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR,
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SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
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value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) |
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(value << SYSCFG_CMPCR_RANSRC_SHIFT);
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mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL);
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mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENCLRR, SYSCFG_CMPENSETR_MPU_EN);
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disable_io_comp_cell(SYSCFG_CMPCR);
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clk_disable(SYSCFG);
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}
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