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feat(qemu-sbsa): handle GIC base

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QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I383919bd172acc8873292a0c5e4469651dc96fb9
This commit is contained in:
Marcin Juszkiewicz 2023-05-15 11:07:54 +02:00
parent c681d02c6c
commit 1e67b1b17a
4 changed files with 126 additions and 2 deletions
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2
plat/qemu/qemu_sbsa/include/platform_def.h
View file

@ -215,6 +215,8 @@
/*
* GIC related constants
* We use GICv3 where CPU Interface registers are not memory mapped
*
* Legacy values - on platform version 0.1+ they are read from DT
*/
#define GICD_BASE 0x40060000
#define GICR_BASE 0x40080000

4
plat/qemu/qemu_sbsa/platform.mk
View file

@ -89,13 +89,13 @@ endif
include drivers/arm/gic/v3/gicv3.mk
QEMU_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c
plat/common/plat_gicv3.c
BL31_SOURCES += ${QEMU_CPU_LIBS} \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
plat/common/plat_psci_common.c \
${PLAT_QEMU_PATH}/sbsa_gic.c \
${PLAT_QEMU_PATH}/sbsa_pm.c \
${PLAT_QEMU_PATH}/sbsa_sip_svc.c \
${PLAT_QEMU_PATH}/sbsa_topology.c \

67
plat/qemu/qemu_sbsa/sbsa_gic.c Normal file
View file

@ -0,0 +1,67 @@
/*
* Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <drivers/arm/gicv3.h>
#include <plat/common/platform.h>
static const interrupt_prop_t qemu_interrupt_props[] = {
PLATFORM_G1S_PROPS(INTR_GROUP1S),
PLATFORM_G0_PROPS(INTR_GROUP0)
};
static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT];
static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr)
{
return plat_core_pos_by_mpidr(mpidr);
}
static gicv3_driver_data_t sbsa_gic_driver_data = {
/* we set those two values for compatibility with older QEMU */
.gicd_base = GICD_BASE,
.gicr_base = GICR_BASE,
.interrupt_props = qemu_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,
.rdistif_base_addrs = qemu_rdistif_base_addrs,
.mpidr_to_core_pos = qemu_mpidr_to_core_pos
};
void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base)
{
sbsa_gic_driver_data.gicd_base = gicd_base;
sbsa_gic_driver_data.gicr_base = gicr_base;
}
uintptr_t sbsa_get_gicd(void)
{
return sbsa_gic_driver_data.gicd_base;
}
uintptr_t sbsa_get_gicr(void)
{
return sbsa_gic_driver_data.gicr_base;
}
void plat_qemu_gic_init(void)
{
gicv3_driver_init(&sbsa_gic_driver_data);
gicv3_distif_init();
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
}
void qemu_pwr_gic_on_finish(void)
{
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
}
void qemu_pwr_gic_off(void)
{
gicv3_cpuif_disable(plat_my_core_pos());
gicv3_rdistif_off(plat_my_core_pos());
}

55
plat/qemu/qemu_sbsa/sbsa_sip_svc.c
View file

@ -6,6 +6,7 @@
#include <assert.h>
#include <common/fdt_wrappers.h>
#include <common/runtime_svc.h>
#include <libfdt.h>
#include <smccc_helpers.h>
@ -26,6 +27,55 @@ static int platform_version_minor;
*/
#define SIP_SVC_VERSION SIP_FUNCTION_ID(1)
#define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100)
void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base);
uintptr_t sbsa_get_gicd(void);
uintptr_t sbsa_get_gicr(void);
void read_platform_config_from_dt(void *dtb)
{
int node;
const fdt64_t *data;
int err;
uintptr_t gicd_base;
uintptr_t gicr_base;
/*
* QEMU gives us this DeviceTree node:
*
* intc {
reg = < 0x00 0x40060000 0x00 0x10000
0x00 0x40080000 0x00 0x4000000>;
};
*/
node = fdt_path_offset(dtb, "/intc");
if (node < 0) {
return;
}
data = fdt_getprop(dtb, node, "reg", NULL);
if (data == NULL) {
return;
}
err = fdt_get_reg_props_by_index(dtb, node, 0, &gicd_base, NULL);
if (err < 0) {
ERROR("Failed to read GICD reg property of GIC node\n");
return;
}
INFO("GICD base = 0x%lx\n", gicd_base);
err = fdt_get_reg_props_by_index(dtb, node, 1, &gicr_base, NULL);
if (err < 0) {
ERROR("Failed to read GICR reg property of GIC node\n");
return;
}
INFO("GICR base = 0x%lx\n", gicr_base);
sbsa_set_gic_bases(gicd_base, gicr_base);
}
void read_platform_version(void *dtb)
{
int node;
@ -60,6 +110,8 @@ void sip_svc_init(void)
read_platform_version(dtb);
INFO("Platform version: %d.%d\n", platform_version_major, platform_version_minor);
read_platform_config_from_dt(dtb);
}
/*
@ -88,6 +140,9 @@ uintptr_t sbsa_sip_smc_handler(uint32_t smc_fid,
INFO("Platform version requested\n");
SMC_RET3(handle, NULL, platform_version_major, platform_version_minor);
case SIP_SVC_GET_GIC:
SMC_RET3(handle, NULL, sbsa_get_gicd(), sbsa_get_gicr());
default:
ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid,
smc_fid - SIP_FUNCTION);