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refactor(sgi): rewrite address space size definitions

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The value of the macro CSS_SGI_REMOTE_CHIP_MEM_OFFSET can be different
across all the Neoverse reference design platforms. This value depends
on the number of address bits used per chip. So let all platforms define
CSS_SGI_ADDR_BITS_PER_CHIP which specifies the number of address bits
used per chip.

In addition to this, reuse the definition of CSS_SGI_ADDR_BITS_PER_CHIP
for single chip platforms and CSS_SGI_REMOTE_CHIP_MEM_OFFSET for multi-
chip platforms to determine the maximum address space size. Also,
increase the RD-N2 multi-chip address space per chip from 4TB to 64TB.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If5e69ec26c2389304c71911729d4addbdf8b2686
This commit is contained in:
Vijayenthiran Subramaniam 2022-01-25 20:37:20 +05:30
parent f9bebcef24
commit 1d74b4bbba
7 changed files with 39 additions and 20 deletions
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9
plat/arm/board/rde1edge/include/platform_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2021, Arm Limited. All rights reserved. * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -26,12 +26,15 @@
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3
/* Maximum number of address bits used per chip */
#define CSS_SGI_ADDR_BITS_PER_CHIP U(36)
/* /*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/ */
#ifdef __aarch64__ #ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
#else #else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)

11
plat/arm/board/rdn1edge/include/platform_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -30,12 +30,17 @@
/* Virtual address used by dynamic mem_protect for chunk_base */ /* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
/* Maximum number of address bits used per chip */
#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
/* /*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/ */
#ifdef __aarch64__ #ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) #define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) CSS_SGI_CHIP_COUNT)
#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT)
#else #else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)

11
plat/arm/board/rdn2/include/platform_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -69,15 +69,16 @@
*/ */
#ifdef __aarch64__ #ifdef __aarch64__
#if (CSS_SGI_PLATFORM_VARIANT == 2) #if (CSS_SGI_PLATFORM_VARIANT == 2)
#define CSS_SGI_ADDR_BITS_PER_CHIP U(46) /* 64TB */
#else
#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) /* 4TB */
#endif
#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ #define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT) CSS_SGI_CHIP_COUNT)
#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ #define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT) CSS_SGI_CHIP_COUNT)
#else #else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42)
#endif
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif #endif

9
plat/arm/board/rdv1/include/platform_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -46,12 +46,15 @@
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
/* Maximum number of address bits used per chip */
#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
/* /*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/ */
#ifdef __aarch64__ #ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
#else #else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)

5
plat/arm/board/rdv1mc/include/platform_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -46,6 +46,9 @@
/* Virtual address used by dynamic mem_protect for chunk_base */ /* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
/* Remote chip address offset (4TB per chip) */
#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
/* Physical and virtual address space limits for MMU in AARCH64 mode */ /* Physical and virtual address space limits for MMU in AARCH64 mode */
#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ #define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT) CSS_SGI_CHIP_COUNT)

9
plat/arm/board/sgi575/include/platform_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -27,12 +27,15 @@
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* Maximum number of address bits used per chip */
#define CSS_SGI_ADDR_BITS_PER_CHIP U(36)
/* /*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/ */
#ifdef __aarch64__ #ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
#else #else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)

5
plat/arm/css/sgi/include/sgi_base_platform_def.h
View file

@ -21,8 +21,9 @@
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
/* Remote chip address offset (4TB per chip) */ /* Remote chip address offset */
#define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) ((ULL(1) << 42) * (n)) #define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) \
((ULL(1) << CSS_SGI_ADDR_BITS_PER_CHIP) * (n))
/* /*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the