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Merge changes from topic "refactor-hw-config-load" into integration

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* changes:
  docs(fvp): update loading addresses of HW_CONFIG
  docs(fconf): update device tree binding for FCONF
  feat(fvp): update HW_CONFIG DT loading mechanism
  refactor(st): update set_config_info function call
  refactor(fvp_r): update set_config_info function call
  refactor(arm): update set_config_info function call
  feat(fconf): add NS load address in configuration DTB nodes
This commit is contained in:
Lauren Wehrmeister 2022-05-03 17:06:49 +02:00 • committed by TrustedFirmware Code Review
commit 1ced6cad52
16 changed files with 247 additions and 69 deletions
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7
docs/components/fconf/fconf_properties.rst
View file

@ -30,3 +30,10 @@ contains, and must be formed with the following fields:
- value type: <u32>
- Image ID of the configuration.
- ns-load-address [optional]
- value type: <u64>
- Physical loading base address of the configuration in the non-secure
memory.
Only needed by those configuration files which require being loaded
in secure memory (at load-address) as well as in non-secure memory
e.g. HW_CONFIG

40
docs/design/firmware-design.rst
View file

@ -131,6 +131,9 @@ convention:
- For other BL3x images, if the firmware configuration file is loaded by
BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded
then its address is passed in ``arg1``.
- In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to
BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved
from FW_CONFIG device tree.
BL1
~~~
@ -1757,12 +1760,20 @@ BL image during boot.
DRAM
0xffffffff +----------+
: :
|----------|
0x82100000 |----------|
|HW_CONFIG |
0x83000000 |----------| (non-secure)
0x82000000 |----------| (non-secure)
| |
0x80000000 +----------+
Trusted DRAM
0x08000000 +----------+
|HW_CONFIG |
0x07f00000 |----------|
: :
| |
0x06000000 +----------+
Trusted SRAM
0x04040000 +----------+ loaded by BL2 +----------------+
| BL1 (rw) | <<<<<<<<<<<<< | |
@ -1790,15 +1801,18 @@ BL image during boot.
DRAM
0xffffffff +--------------+
: :
|--------------|
0x82100000 |--------------|
| HW_CONFIG |
0x83000000 |--------------| (non-secure)
0x82000000 |--------------| (non-secure)
| |
0x80000000 +--------------+
Trusted DRAM
Trusted DRAM
0x08000000 +--------------+
| BL32 |
| HW_CONFIG |
0x07f00000 |--------------|
: :
| BL32 |
0x06000000 +--------------+
Trusted SRAM
@ -1829,12 +1843,20 @@ BL image during boot.
| BL32 | (secure)
0xff000000 +----------+
| |
|----------|
0x82100000 |----------|
|HW_CONFIG |
0x83000000 |----------| (non-secure)
0x82000000 |----------| (non-secure)
| |
0x80000000 +----------+
Trusted DRAM
0x08000000 +----------+
|HW_CONFIG |
0x7f000000 |----------|
: :
| |
0x06000000 +----------+
Trusted SRAM
0x04040000 +----------+ loaded by BL2 +----------------+
| BL1 (rw) | <<<<<<<<<<<<< | |
@ -2729,7 +2751,7 @@ kernel at boot time. These can be found in the ``fdts`` directory.
--------------
*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.*
*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
.. _SMCCC: https://developer.arm.com/docs/den0028/latest

14
include/lib/fconf/fconf_dyn_cfg_getter.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, Arm Limited. All rights reserved.
* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -18,6 +18,13 @@ struct dyn_cfg_dtb_info_t {
uintptr_t config_addr;
uint32_t config_max_size;
unsigned int config_id;
/*
* Load address in non-secure memory. Only needed by those
* configuration files which require being loaded in secure
* memory (at config_addr) as well as in non-secure memory
* - e.g. HW_CONFIG
*/
uintptr_t ns_config_addr;
};
unsigned int dyn_cfg_dtb_info_get_index(unsigned int config_id);
@ -25,7 +32,8 @@ struct dyn_cfg_dtb_info_t *dyn_cfg_dtb_info_getter(unsigned int config_id);
int fconf_populate_dtb_registry(uintptr_t config);
/* Set config information in global DTB array */
void set_config_info(uintptr_t config_addr, uint32_t config_max_size,
unsigned int config_id);
void set_config_info(uintptr_t config_addr, uintptr_t ns_config_addr,
uint32_t config_max_size,
unsigned int config_id);
#endif /* FCONF_DYN_CFG_GETTER_H */

2
include/plat/arm/common/arm_def.h
View file

@ -284,12 +284,10 @@
ARM_EL3_TZC_DRAM1_SIZE, \
MT_MEMORY | MT_RW | EL3_PAS)
#if defined(SPD_spmd)
#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \
PLAT_ARM_TRUSTED_DRAM_BASE, \
PLAT_ARM_TRUSTED_DRAM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
#endif
#if ENABLE_RME
#define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \

20
lib/fconf/fconf_dyn_cfg_getter.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, Arm Limited. All rights reserved.
* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -29,13 +29,15 @@ static OBJECT_POOL_ARRAY(dtb_info_pool, dtb_infos);
* This function is used to alloc memory for config information from
* global pool and set the configuration information.
*/
void set_config_info(uintptr_t config_addr, uint32_t config_max_size,
unsigned int config_id)
void set_config_info(uintptr_t config_addr, uintptr_t ns_config_addr,
uint32_t config_max_size,
unsigned int config_id)
{
struct dyn_cfg_dtb_info_t *dtb_info;
dtb_info = pool_alloc(&dtb_info_pool);
dtb_info->config_addr = config_addr;
dtb_info->ns_config_addr = ns_config_addr;
dtb_info->config_max_size = config_max_size;
dtb_info->config_id = config_id;
}
@ -88,7 +90,7 @@ int fconf_populate_dtb_registry(uintptr_t config)
*/
if (dtb_infos[0].config_id == 0U) {
uint32_t config_max_size = fdt_totalsize(dtb);
set_config_info(config, config_max_size, FW_CONFIG_ID);
set_config_info(config, ~0UL, config_max_size, FW_CONFIG_ID);
}
/* Find the node offset point to "fconf,dyn_cfg-dtb_registry" compatible property */
@ -102,6 +104,7 @@ int fconf_populate_dtb_registry(uintptr_t config)
fdt_for_each_subnode(child, dtb, node) {
uint32_t config_max_size, config_id;
uintptr_t config_addr;
uintptr_t ns_config_addr = ~0UL;
uint64_t val64;
/* Read configuration dtb information */
@ -129,7 +132,14 @@ int fconf_populate_dtb_registry(uintptr_t config)
VERBOSE("\tmax-size = 0x%x\n", config_max_size);
VERBOSE("\tconfig-id = %u\n", config_id);
set_config_info(config_addr, config_max_size, config_id);
rc = fdt_read_uint64(dtb, child, "ns-load-address", &val64);
if (rc == 0) {
ns_config_addr = (uintptr_t)val64;
VERBOSE("\tns-load-address = %lx\n", ns_config_addr);
}
set_config_info(config_addr, ns_config_addr, config_max_size,
config_id);
}
if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) {

7
plat/arm/board/fvp/fdts/fvp_fw_config.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, ARM Limited. All rights reserved.
* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -19,9 +19,10 @@
};
hw-config {
load-address = <0x0 0x82000000>;
max-size = <0x01000000>;
load-address = <0x0 0x07f00000>;
max-size = <0x00100000>;
id = <HW_CONFIG_ID>;
ns-load-address = <0x0 0x82000000>;
};
/*

46
plat/arm/board/fvp/fvp_bl2_setup.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -40,17 +40,23 @@ void bl2_platform_setup(void)
struct bl_params *plat_get_next_bl_params(void)
{
struct bl_params *arm_bl_params;
const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
bl_mem_params_node_t *param_node __unused;
arm_bl_params = arm_get_next_bl_params();
#if __aarch64__ && !BL2_AT_EL3
#if !BL2_AT_EL3 && !EL3_PAYLOAD_BASE
const struct dyn_cfg_dtb_info_t *fw_config_info;
bl_mem_params_node_t *param_node;
uintptr_t fw_config_base = 0U;
uintptr_t fw_config_base = 0UL;
entry_point_info_t *ep_info;
#if __aarch64__
/* Get BL31 image node */
param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
#else /* aarch32 */
/* Get SP_MIN image node */
param_node = get_bl_mem_params_node(BL32_IMAGE_ID);
#endif /* __aarch64__ */
assert(param_node != NULL);
/* get fw_config load address */
@ -58,15 +64,41 @@ struct bl_params *plat_get_next_bl_params(void)
assert(fw_config_info != NULL);
fw_config_base = fw_config_info->config_addr;
assert(fw_config_base != 0U);
assert(fw_config_base != 0UL);
/*
* Get the entry point info of BL31 image and override
* Get the entry point info of next executable image and override
* arg1 of entry point info with fw_config base address
*/
ep_info = &param_node->ep_info;
ep_info->args.arg1 = (uint32_t)fw_config_base;
#endif /* __aarch64__ && !BL2_AT_EL3 */
/* grab NS HW config address */
hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
/* To retrieve actual size of the HW_CONFIG */
param_node = get_bl_mem_params_node(HW_CONFIG_ID);
assert(param_node != NULL);
/* Copy HW config from Secure address to NS address */
memcpy((void *)hw_config_info->ns_config_addr,
(void *)hw_config_info->config_addr,
(size_t)param_node->image_info.image_size);
/*
* Ensure HW-config device tree committed to memory, as there is
* a possibility to use HW-config without cache and MMU enabled
* at BL33
*/
flush_dcache_range(hw_config_info->ns_config_addr,
param_node->image_info.image_size);
param_node = get_bl_mem_params_node(BL33_IMAGE_ID);
assert(param_node != NULL);
/* Update BL33's ep info with NS HW config address */
param_node->ep_info.args.arg1 = hw_config_info->ns_config_addr;
#endif /* !BL2_AT_EL3 && !EL3_PAYLOAD_BASE */
return arm_bl_params;
}

62
plat/arm/board/fvp/fvp_bl31_setup.c
View file

@ -17,6 +17,8 @@
#include "fvp_private.h"
static const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
void __init bl31_early_platform_setup2(u_register_t arg0,
u_register_t arg1, u_register_t arg2, u_register_t arg3)
{
@ -34,6 +36,17 @@ void __init bl31_early_platform_setup2(u_register_t arg0,
if (soc_fw_config_info != NULL) {
arg1 = soc_fw_config_info->config_addr;
}
/*
* arg2 is currently holding the 'secure' address of HW_CONFIG.
* But arm_bl31_early_platform_setup() below expects the 'non-secure'
* address of HW_CONFIG (which it will pass to BL33).
* This why we need to override arg2 here.
*/
hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
assert(hw_config_info != NULL);
assert(hw_config_info->ns_config_addr != 0UL);
arg2 = hw_config_info->ns_config_addr;
#endif /* !RESET_TO_BL31 && !BL2_AT_EL3 */
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
@ -66,22 +79,57 @@ void __init bl31_early_platform_setup2(u_register_t arg0,
void __init bl31_plat_arch_setup(void)
{
int rc __unused;
uintptr_t hw_config_base_align __unused;
size_t mapped_size_align __unused;
arm_bl31_plat_arch_setup();
/*
* For RESET_TO_BL31 systems, BL31 is the first bootloader to run.
* So there is no BL2 to load the HW_CONFIG dtb into memory before
* control is passed to BL31.
* control is passed to BL31. The code below relies on dynamic mapping
* capability, which is not supported by xlat tables lib V1.
* TODO: remove the ARM_XLAT_TABLES_LIB_V1 check when its support
* gets deprecated.
*/
#if !RESET_TO_BL31 && !BL2_AT_EL3
/* HW_CONFIG was also loaded by BL2 */
const struct dyn_cfg_dtb_info_t *hw_config_info;
hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
#if !RESET_TO_BL31 && !BL2_AT_EL3 && !ARM_XLAT_TABLES_LIB_V1
assert(hw_config_info != NULL);
assert(hw_config_info->config_addr != 0UL);
/* Page aligned address and size if necessary */
hw_config_base_align = page_align(hw_config_info->config_addr, DOWN);
mapped_size_align = page_align(hw_config_info->config_max_size, UP);
if ((hw_config_info->config_addr != hw_config_base_align) &&
(hw_config_info->config_max_size == mapped_size_align)) {
mapped_size_align += PAGE_SIZE;
}
/*
* map dynamically HW config region with its aligned base address and
* size
*/
rc = mmap_add_dynamic_region((unsigned long long)hw_config_base_align,
hw_config_base_align,
mapped_size_align,
MT_RO_DATA);
if (rc != 0) {
ERROR("Error while mapping HW_CONFIG device tree (%d).\n", rc);
panic();
}
/* Populate HW_CONFIG device tree with the mapped address */
fconf_populate("HW_CONFIG", hw_config_info->config_addr);
#endif
/* unmap the HW_CONFIG memory region */
rc = mmap_remove_dynamic_region(hw_config_base_align, mapped_size_align);
if (rc != 0) {
ERROR("Error while unmapping HW_CONFIG device tree (%d).\n",
rc);
panic();
}
#endif /* !RESET_TO_BL31 && !BL2_AT_EL3 && !ARM_XLAT_TABLES_LIB_V1 */
}
unsigned int plat_get_syscnt_freq2(void)

9
plat/arm/board/fvp/fvp_common.c
View file

@ -104,9 +104,10 @@ const mmap_region_t plat_arm_mmap[] = {
#ifdef __aarch64__
ARM_MAP_DRAM2,
#endif
#if defined(SPD_spmd)
/*
* Required to load HW_CONFIG, SPMC and SPs to trusted DRAM.
*/
ARM_MAP_TRUSTED_DRAM,
#endif
#if ENABLE_RME
ARM_MAP_RMM_DRAM,
ARM_MAP_GPT_L1_DRAM,
@ -166,8 +167,6 @@ const mmap_region_t plat_arm_mmap[] = {
#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif
/* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
ARM_DTB_DRAM_NS,
#if ENABLE_RME
ARM_MAP_GPT_L1_DRAM,
#endif
@ -197,8 +196,6 @@ const mmap_region_t plat_arm_mmap[] = {
V2M_MAP_IOFPGA,
MAP_DEVICE0,
MAP_DEVICE1,
/* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
ARM_DTB_DRAM_NS,
{0}
};
#endif

4
plat/arm/board/fvp/include/platform_def.h
View file

@ -86,10 +86,6 @@
#define FVP_DTB_DRAM_MAP_START ULL(0x82000000)
#define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */
#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \
FVP_DTB_DRAM_MAP_START, \
FVP_DTB_DRAM_MAP_SIZE, \
MT_MEMORY | MT_RO | MT_NS)
/*
* Load address of BL33 for this platform port
*/

11
plat/arm/board/fvp/platform.mk
View file

@ -333,15 +333,10 @@ ifeq (${ARCH},aarch32)
endif
# Enable the dynamic translation tables library.
ifeq (${ARCH},aarch32)
ifeq (${RESET_TO_SP_MIN},1)
ifeq ($(filter 1,${BL2_AT_EL3} ${ARM_XLAT_TABLES_LIB_V1}),)
ifeq (${ARCH},aarch32)
BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
endif
else # AArch64
ifeq (${RESET_TO_BL31},1)
BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
endif
ifeq (${SPD},trusty)
else # AArch64
BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
endif
endif

81
plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,15 +9,31 @@
#include <bl32/sp_min/platform_sp_min.h>
#include <common/debug.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <plat/arm/common/plat_arm.h>
#include "../fvp_private.h"
uintptr_t hw_config_dtb;
void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
const struct dyn_cfg_dtb_info_t *tos_fw_config_info __unused;
/* Initialize the console to provide early debug support */
arm_console_boot_init();
#if !RESET_TO_SP_MIN && !BL2_AT_EL3
INFO("SP_MIN FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1);
/* Fill the properties struct with the info from the config dtb */
fconf_populate("FW_CONFIG", arg1);
tos_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TOS_FW_CONFIG_ID);
if (tos_fw_config_info != NULL) {
arg1 = tos_fw_config_info->config_addr;
}
#endif /* !RESET_TO_SP_MIN && !BL2_AT_EL3 */
arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
/* Initialize the platform config for future decision making */
@ -37,12 +53,15 @@ void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
* FVP PSCI code will enable coherency for other clusters.
*/
fvp_interconnect_enable();
hw_config_dtb = arg2;
}
void sp_min_plat_arch_setup(void)
{
int rc __unused;
const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
uintptr_t hw_config_base_align __unused;
size_t mapped_size_align __unused;
arm_sp_min_plat_arch_setup();
/*
@ -50,11 +69,53 @@ void sp_min_plat_arch_setup(void)
* to run. So there is no BL2 to load the HW_CONFIG dtb into memory
* before control is passed to SP_MIN.
* Also, BL2 skips loading HW_CONFIG dtb for BL2_AT_EL3 builds.
* The code below relies on dynamic mapping capability, which is not
* supported by xlat tables lib V1.
* TODO: remove the ARM_XLAT_TABLES_LIB_V1 check when its support
* gets deprecated.
*/
#if !RESET_TO_SP_MIN && !BL2_AT_EL3
assert(hw_config_dtb != 0U);
#if !RESET_TO_SP_MIN && !BL2_AT_EL3 && !ARM_XLAT_TABLES_LIB_V1
hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
assert(hw_config_info != NULL);
assert(hw_config_info->config_addr != 0UL);
INFO("SP_MIN FCONF: HW_CONFIG address = %p\n", (void *)hw_config_dtb);
fconf_populate("HW_CONFIG", hw_config_dtb);
#endif
INFO("SP_MIN FCONF: HW_CONFIG address = %p\n",
(void *)hw_config_info->config_addr);
/*
* Preferrably we expect this address and size are page aligned,
* but if they are not then align it.
*/
hw_config_base_align = page_align(hw_config_info->config_addr, DOWN);
mapped_size_align = page_align(hw_config_info->config_max_size, UP);
if ((hw_config_info->config_addr != hw_config_base_align) &&
(hw_config_info->config_max_size == mapped_size_align)) {
mapped_size_align += PAGE_SIZE;
}
/*
* map dynamically HW config region with its aligned base address and
* size
*/
rc = mmap_add_dynamic_region((unsigned long long)hw_config_base_align,
hw_config_base_align,
mapped_size_align,
MT_RO_DATA);
if (rc != 0) {
ERROR("Error while mapping HW_CONFIG device tree (%d).\n", rc);
panic();
}
/* Populate HW_CONFIG device tree with the mapped address */
fconf_populate("HW_CONFIG", hw_config_info->config_addr);
/* unmap the HW_CONFIG memory region */
rc = mmap_remove_dynamic_region(hw_config_base_align, mapped_size_align);
if (rc != 0) {
ERROR("Error while unmapping HW_CONFIG device tree (%d).\n",
rc);
panic();
}
#endif /* !RESET_TO_SP_MIN && !BL2_AT_EL3 && !ARM_XLAT_TABLES_LIB_V1 */
}

5
plat/arm/board/fvp/sp_min/sp_min-fvp.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -25,7 +25,8 @@ BL32_SOURCES += drivers/arm/fvp/fvp_pwrc.c \
# Added separately from the above list for better readability
ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_SP_MIN}),)
BL32_SOURCES += lib/fconf/fconf.c \
plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
lib/fconf/fconf_dyn_cfg_getter.c \
plat/arm/board/fvp/fconf/fconf_hw_config_getter.c \
BL32_SOURCES += ${FDT_WRAPPERS_SOURCES}

3
plat/arm/board/fvp_r/fvp_r_bl1_setup.c
View file

@ -154,7 +154,8 @@ void arm_bl1_platform_setup(void)
/* Set global DTB info for fixed fw_config information */
fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
set_config_info(ARM_FW_CONFIG_BASE, fw_config_max_size, FW_CONFIG_ID);
set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size,
FW_CONFIG_ID);
assert(bl1_plat_get_image_desc(BL33_IMAGE_ID) != NULL);

2
plat/arm/common/arm_bl1_setup.c
View file

@ -166,7 +166,7 @@ void arm_bl1_platform_setup(void)
/* Set global DTB info for fixed fw_config information */
fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
set_config_info(ARM_FW_CONFIG_BASE, fw_config_max_size, FW_CONFIG_ID);
set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID);
/* Fill the device tree information struct with the info from the config dtb */
err = fconf_load_config(FW_CONFIG_ID);

3
plat/st/stm32mp1/bl2_plat_setup.c
View file

@ -432,7 +432,8 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
#if !STM32MP_USE_STM32IMAGE
case FW_CONFIG_ID:
/* Set global DTB info for fixed fw_config information */
set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID);
set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE,
FW_CONFIG_ID);
fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID);