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Add support for ARM Cortex-A72 processor
This patch adds support for ARM Cortex-A72 processor in the CPU specific framework. Change-Id: I5986855fc1b875aadf3eba8c36e989d8a05e5175
This commit is contained in:
Vikram Kanigiri
parent
b5b12347ab
commit
1ba93aeb89
2 changed files with 301 additions and 0 deletions
67
include/lib/cpus/aarch64/cortex_a72.h
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67
include/lib/cpus/aarch64/cortex_a72.h
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CORTEX_A72_H__
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#define __CORTEX_A72_H__
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/* Cortex-A72 midr for revision 0 */
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#define CORTEX_A72_MIDR 0x410FD080
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
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#define CPUECTLR_SMP_BIT (1 << 6)
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#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
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#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
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#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */
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#define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
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#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
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#define CPUACTLR_DCC_AS_DCCI (1 << 44)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */
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#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
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#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
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#endif /* __CORTEX_A72_H__ */
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234
lib/cpus/aarch64/cortex_a72.S
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234
lib/cpus/aarch64/cortex_a72.S
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a72.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func cortex_a72_disable_dcache
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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ret
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/* ---------------------------------------------
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* Disable all types of L2 prefetches.
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* ---------------------------------------------
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*/
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func cortex_a72_disable_l2_prefetch
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mrs x0, CPUECTLR_EL1
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orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
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mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK
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orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK
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bic x0, x0, x1
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msr CPUECTLR_EL1, x0
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isb
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ret
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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func cortex_a72_disable_hw_prefetcher
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mrs x0, CPUACTLR_EL1
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orr x0, x0, #CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
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msr CPUACTLR_EL1, x0
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isb
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dsb ish
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ret
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a72_disable_smp
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mrs x0, CPUECTLR_EL1
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bic x0, x0, #CPUECTLR_SMP_BIT
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msr CPUECTLR_EL1, x0
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ret
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/* ---------------------------------------------
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* Disable debug interfaces
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* ---------------------------------------------
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*/
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func cortex_a72_disable_ext_debug
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mov x0, #1
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msr osdlr_el1, x0
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isb
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dsb sy
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ret
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A72.
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* -------------------------------------------------
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*/
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func cortex_a72_reset_func
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/* ---------------------------------------------
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* As a bare minimum enable the SMP bit.
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* ---------------------------------------------
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*/
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mrs x0, CPUECTLR_EL1
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orr x0, x0, #CPUECTLR_SMP_BIT
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msr CPUECTLR_EL1, x0
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isb
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ret
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A72.
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* ----------------------------------------------------
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*/
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func cortex_a72_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_dcache
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_hw_prefetcher
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_smp
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a72_disable_ext_debug
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Cortex-A72.
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* -------------------------------------------------------
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*/
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func cortex_a72_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_dcache
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_hw_prefetcher
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#if !SKIP_A72_L1_FLUSH_PWR_DWN
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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#endif
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* -------------------------------------------------
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* Flush the L2 caches.
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* -------------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_smp
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a72_disable_ext_debug
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/* ---------------------------------------------
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* This function provides cortex_a72 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a72_regs, "aS"
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cortex_a72_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a72_cpu_reg_dump
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adr x6, cortex_a72_regs
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mrs x8, CPUECTLR_EL1
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ret
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declare_cpu_ops cortex_a72, CORTEX_A72_MIDR
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