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feat(dt-bindings): add bindings for STM32MP13

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Add dedicated clock and reset dt-bindings include files. The former
files are renamed with stm32mp15, and the stm32mp1 file just
determine through STM32MP13 or STM32MP15 flag which file to include.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I0db23996a3ba25f7c3ea920f16230b11cf051208
This commit is contained in:
Yann Gautier 2022-03-10 11:33:13 +01:00
parent 6512c3a62a
commit 1b8898eb32
9 changed files with 1424 additions and 669 deletions
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280
include/dt-bindings/clock/stm32mp1-clks.h
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@ -1,278 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/* /*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved * Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/ */
#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ #if STM32MP13
#define _DT_BINDINGS_STM32MP1_CLKS_H_ #include "stm32mp13-clks.h"
#endif
/* OSCILLATOR clocks */ #if STM32MP15
#define CK_HSE 0 #include "stm32mp15-clks.h"
#define CK_CSI 1 #endif
#define CK_LSI 2
#define CK_LSE 3
#define CK_HSI 4
#define CK_HSE_DIV2 5
/* Bus clocks */
#define TIM2 6
#define TIM3 7
#define TIM4 8
#define TIM5 9
#define TIM6 10
#define TIM7 11
#define TIM12 12
#define TIM13 13
#define TIM14 14
#define LPTIM1 15
#define SPI2 16
#define SPI3 17
#define USART2 18
#define USART3 19
#define UART4 20
#define UART5 21
#define UART7 22
#define UART8 23
#define I2C1 24
#define I2C2 25
#define I2C3 26
#define I2C5 27
#define SPDIF 28
#define CEC 29
#define DAC12 30
#define MDIO 31
#define TIM1 32
#define TIM8 33
#define TIM15 34
#define TIM16 35
#define TIM17 36
#define SPI1 37
#define SPI4 38
#define SPI5 39
#define USART6 40
#define SAI1 41
#define SAI2 42
#define SAI3 43
#define DFSDM 44
#define FDCAN 45
#define LPTIM2 46
#define LPTIM3 47
#define LPTIM4 48
#define LPTIM5 49
#define SAI4 50
#define SYSCFG 51
#define VREF 52
#define TMPSENS 53
#define PMBCTRL 54
#define HDP 55
#define LTDC 56
#define DSI 57
#define IWDG2 58
#define USBPHY 59
#define STGENRO 60
#define SPI6 61
#define I2C4 62
#define I2C6 63
#define USART1 64
#define RTCAPB 65
#define TZC1 66
#define TZPC 67
#define IWDG1 68
#define BSEC 69
#define STGEN 70
#define DMA1 71
#define DMA2 72
#define DMAMUX 73
#define ADC12 74
#define USBO 75
#define SDMMC3 76
#define DCMI 77
#define CRYP2 78
#define HASH2 79
#define RNG2 80
#define CRC2 81
#define HSEM 82
#define IPCC 83
#define GPIOA 84
#define GPIOB 85
#define GPIOC 86
#define GPIOD 87
#define GPIOE 88
#define GPIOF 89
#define GPIOG 90
#define GPIOH 91
#define GPIOI 92
#define GPIOJ 93
#define GPIOK 94
#define GPIOZ 95
#define CRYP1 96
#define HASH1 97
#define RNG1 98
#define BKPSRAM 99
#define MDMA 100
#define GPU 101
#define ETHCK 102
#define ETHTX 103
#define ETHRX 104
#define ETHMAC 105
#define FMC 106
#define QSPI 107
#define SDMMC1 108
#define SDMMC2 109
#define CRC1 110
#define USBH 111
#define ETHSTP 112
#define TZC2 113
/* Kernel clocks */
#define SDMMC1_K 118
#define SDMMC2_K 119
#define SDMMC3_K 120
#define FMC_K 121
#define QSPI_K 122
#define ETHCK_K 123
#define RNG1_K 124
#define RNG2_K 125
#define GPU_K 126
#define USBPHY_K 127
#define STGEN_K 128
#define SPDIF_K 129
#define SPI1_K 130
#define SPI2_K 131
#define SPI3_K 132
#define SPI4_K 133
#define SPI5_K 134
#define SPI6_K 135
#define CEC_K 136
#define I2C1_K 137
#define I2C2_K 138
#define I2C3_K 139
#define I2C4_K 140
#define I2C5_K 141
#define I2C6_K 142
#define LPTIM1_K 143
#define LPTIM2_K 144
#define LPTIM3_K 145
#define LPTIM4_K 146
#define LPTIM5_K 147
#define USART1_K 148
#define USART2_K 149
#define USART3_K 150
#define UART4_K 151
#define UART5_K 152
#define USART6_K 153
#define UART7_K 154
#define UART8_K 155
#define DFSDM_K 156
#define FDCAN_K 157
#define SAI1_K 158
#define SAI2_K 159
#define SAI3_K 160
#define SAI4_K 161
#define ADC12_K 162
#define DSI_K 163
#define DSI_PX 164
#define ADFSDM_K 165
#define USBO_K 166
#define LTDC_PX 167
#define DAC12_K 168
#define ETHPTP_K 169
/* PLL */
#define PLL1 176
#define PLL2 177
#define PLL3 178
#define PLL4 179
/* ODF */
#define PLL1_P 180
#define PLL1_Q 181
#define PLL1_R 182
#define PLL2_P 183
#define PLL2_Q 184
#define PLL2_R 185
#define PLL3_P 186
#define PLL3_Q 187
#define PLL3_R 188
#define PLL4_P 189
#define PLL4_Q 190
#define PLL4_R 191
/* AUX */
#define RTC 192
/* MCLK */
#define CK_PER 193
#define CK_MPU 194
#define CK_AXI 195
#define CK_MCU 196
/* Time base */
#define TIM2_K 197
#define TIM3_K 198
#define TIM4_K 199
#define TIM5_K 200
#define TIM6_K 201
#define TIM7_K 202
#define TIM12_K 203
#define TIM13_K 204
#define TIM14_K 205
#define TIM1_K 206
#define TIM8_K 207
#define TIM15_K 208
#define TIM16_K 209
#define TIM17_K 210
/* MCO clocks */
#define CK_MCO1 211
#define CK_MCO2 212
/* TRACE & DEBUG clocks */
#define CK_DBG 214
#define CK_TRACE 215
/* DDR */
#define DDRC1 220
#define DDRC1LP 221
#define DDRC2 222
#define DDRC2LP 223
#define DDRPHYC 224
#define DDRPHYCLP 225
#define DDRCAPB 226
#define DDRCAPBLP 227
#define AXIDCG 228
#define DDRPHYCAPB 229
#define DDRPHYCAPBLP 230
#define DDRPERFM 231
#define STM32MP1_LAST_CLK 232
/* SCMI clock identifiers */
#define CK_SCMI0_HSE 0
#define CK_SCMI0_HSI 1
#define CK_SCMI0_CSI 2
#define CK_SCMI0_LSE 3
#define CK_SCMI0_LSI 4
#define CK_SCMI0_PLL2_Q 5
#define CK_SCMI0_PLL2_R 6
#define CK_SCMI0_MPU 7
#define CK_SCMI0_AXI 8
#define CK_SCMI0_BSEC 9
#define CK_SCMI0_CRYP1 10
#define CK_SCMI0_GPIOZ 11
#define CK_SCMI0_HASH1 12
#define CK_SCMI0_I2C4 13
#define CK_SCMI0_I2C6 14
#define CK_SCMI0_IWDG1 15
#define CK_SCMI0_RNG1 16
#define CK_SCMI0_RTC 17
#define CK_SCMI0_RTCAPB 18
#define CK_SCMI0_SPI6 19
#define CK_SCMI0_USART1 20
#define CK_SCMI1_PLL3_Q 0
#define CK_SCMI1_PLL3_R 1
#define CK_SCMI1_MCU 2
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */

284
include/dt-bindings/clock/stm32mp1-clksrc.h
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@ -1,283 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/* /*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved * Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved
*/ */
#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ #if STM32MP13
#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ #include "stm32mp13-clksrc.h"
#endif
/* PLL output is enable when x=1, with x=p,q or r */ #if STM32MP15
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) #include "stm32mp15-clksrc.h"
/* st,clksrc: mandatory clock source */
#define CLK_MPU_HSI 0x00000200
#define CLK_MPU_HSE 0x00000201
#define CLK_MPU_PLL1P 0x00000202
#define CLK_MPU_PLL1P_DIV 0x00000203
#define CLK_AXI_HSI 0x00000240
#define CLK_AXI_HSE 0x00000241
#define CLK_AXI_PLL2P 0x00000242
#define CLK_MCU_HSI 0x00000480
#define CLK_MCU_HSE 0x00000481
#define CLK_MCU_CSI 0x00000482
#define CLK_MCU_PLL3P 0x00000483
#define CLK_PLL12_HSI 0x00000280
#define CLK_PLL12_HSE 0x00000281
#define CLK_PLL3_HSI 0x00008200
#define CLK_PLL3_HSE 0x00008201
#define CLK_PLL3_CSI 0x00008202
#define CLK_PLL4_HSI 0x00008240
#define CLK_PLL4_HSE 0x00008241
#define CLK_PLL4_CSI 0x00008242
#define CLK_PLL4_I2SCKIN 0x00008243
#define CLK_RTC_DISABLED 0x00001400
#define CLK_RTC_LSE 0x00001401
#define CLK_RTC_LSI 0x00001402
#define CLK_RTC_HSE 0x00001403
#define CLK_MCO1_HSI 0x00008000
#define CLK_MCO1_HSE 0x00008001
#define CLK_MCO1_CSI 0x00008002
#define CLK_MCO1_LSI 0x00008003
#define CLK_MCO1_LSE 0x00008004
#define CLK_MCO1_DISABLED 0x0000800F
#define CLK_MCO2_MPU 0x00008040
#define CLK_MCO2_AXI 0x00008041
#define CLK_MCO2_MCU 0x00008042
#define CLK_MCO2_PLL4P 0x00008043
#define CLK_MCO2_HSE 0x00008044
#define CLK_MCO2_HSI 0x00008045
#define CLK_MCO2_DISABLED 0x0000804F
/* st,pkcs: peripheral kernel clock source */
#define CLK_I2C12_PCLK1 0x00008C00
#define CLK_I2C12_PLL4R 0x00008C01
#define CLK_I2C12_HSI 0x00008C02
#define CLK_I2C12_CSI 0x00008C03
#define CLK_I2C12_DISABLED 0x00008C07
#define CLK_I2C35_PCLK1 0x00008C40
#define CLK_I2C35_PLL4R 0x00008C41
#define CLK_I2C35_HSI 0x00008C42
#define CLK_I2C35_CSI 0x00008C43
#define CLK_I2C35_DISABLED 0x00008C47
#define CLK_I2C46_PCLK5 0x00000C00
#define CLK_I2C46_PLL3Q 0x00000C01
#define CLK_I2C46_HSI 0x00000C02
#define CLK_I2C46_CSI 0x00000C03
#define CLK_I2C46_DISABLED 0x00000C07
#define CLK_SAI1_PLL4Q 0x00008C80
#define CLK_SAI1_PLL3Q 0x00008C81
#define CLK_SAI1_I2SCKIN 0x00008C82
#define CLK_SAI1_CKPER 0x00008C83
#define CLK_SAI1_PLL3R 0x00008C84
#define CLK_SAI1_DISABLED 0x00008C87
#define CLK_SAI2_PLL4Q 0x00008CC0
#define CLK_SAI2_PLL3Q 0x00008CC1
#define CLK_SAI2_I2SCKIN 0x00008CC2
#define CLK_SAI2_CKPER 0x00008CC3
#define CLK_SAI2_SPDIF 0x00008CC4
#define CLK_SAI2_PLL3R 0x00008CC5
#define CLK_SAI2_DISABLED 0x00008CC7
#define CLK_SAI3_PLL4Q 0x00008D00
#define CLK_SAI3_PLL3Q 0x00008D01
#define CLK_SAI3_I2SCKIN 0x00008D02
#define CLK_SAI3_CKPER 0x00008D03
#define CLK_SAI3_PLL3R 0x00008D04
#define CLK_SAI3_DISABLED 0x00008D07
#define CLK_SAI4_PLL4Q 0x00008D40
#define CLK_SAI4_PLL3Q 0x00008D41
#define CLK_SAI4_I2SCKIN 0x00008D42
#define CLK_SAI4_CKPER 0x00008D43
#define CLK_SAI4_PLL3R 0x00008D44
#define CLK_SAI4_DISABLED 0x00008D47
#define CLK_SPI2S1_PLL4P 0x00008D80
#define CLK_SPI2S1_PLL3Q 0x00008D81
#define CLK_SPI2S1_I2SCKIN 0x00008D82
#define CLK_SPI2S1_CKPER 0x00008D83
#define CLK_SPI2S1_PLL3R 0x00008D84
#define CLK_SPI2S1_DISABLED 0x00008D87
#define CLK_SPI2S23_PLL4P 0x00008DC0
#define CLK_SPI2S23_PLL3Q 0x00008DC1
#define CLK_SPI2S23_I2SCKIN 0x00008DC2
#define CLK_SPI2S23_CKPER 0x00008DC3
#define CLK_SPI2S23_PLL3R 0x00008DC4
#define CLK_SPI2S23_DISABLED 0x00008DC7
#define CLK_SPI45_PCLK2 0x00008E00
#define CLK_SPI45_PLL4Q 0x00008E01
#define CLK_SPI45_HSI 0x00008E02
#define CLK_SPI45_CSI 0x00008E03
#define CLK_SPI45_HSE 0x00008E04
#define CLK_SPI45_DISABLED 0x00008E07
#define CLK_SPI6_PCLK5 0x00000C40
#define CLK_SPI6_PLL4Q 0x00000C41
#define CLK_SPI6_HSI 0x00000C42
#define CLK_SPI6_CSI 0x00000C43
#define CLK_SPI6_HSE 0x00000C44
#define CLK_SPI6_PLL3Q 0x00000C45
#define CLK_SPI6_DISABLED 0x00000C47
#define CLK_UART6_PCLK2 0x00008E40
#define CLK_UART6_PLL4Q 0x00008E41
#define CLK_UART6_HSI 0x00008E42
#define CLK_UART6_CSI 0x00008E43
#define CLK_UART6_HSE 0x00008E44
#define CLK_UART6_DISABLED 0x00008E47
#define CLK_UART24_PCLK1 0x00008E80
#define CLK_UART24_PLL4Q 0x00008E81
#define CLK_UART24_HSI 0x00008E82
#define CLK_UART24_CSI 0x00008E83
#define CLK_UART24_HSE 0x00008E84
#define CLK_UART24_DISABLED 0x00008E87
#define CLK_UART35_PCLK1 0x00008EC0
#define CLK_UART35_PLL4Q 0x00008EC1
#define CLK_UART35_HSI 0x00008EC2
#define CLK_UART35_CSI 0x00008EC3
#define CLK_UART35_HSE 0x00008EC4
#define CLK_UART35_DISABLED 0x00008EC7
#define CLK_UART78_PCLK1 0x00008F00
#define CLK_UART78_PLL4Q 0x00008F01
#define CLK_UART78_HSI 0x00008F02
#define CLK_UART78_CSI 0x00008F03
#define CLK_UART78_HSE 0x00008F04
#define CLK_UART78_DISABLED 0x00008F07
#define CLK_UART1_PCLK5 0x00000C80
#define CLK_UART1_PLL3Q 0x00000C81
#define CLK_UART1_HSI 0x00000C82
#define CLK_UART1_CSI 0x00000C83
#define CLK_UART1_PLL4Q 0x00000C84
#define CLK_UART1_HSE 0x00000C85
#define CLK_UART1_DISABLED 0x00000C87
#define CLK_SDMMC12_HCLK6 0x00008F40
#define CLK_SDMMC12_PLL3R 0x00008F41
#define CLK_SDMMC12_PLL4P 0x00008F42
#define CLK_SDMMC12_HSI 0x00008F43
#define CLK_SDMMC12_DISABLED 0x00008F47
#define CLK_SDMMC3_HCLK2 0x00008F80
#define CLK_SDMMC3_PLL3R 0x00008F81
#define CLK_SDMMC3_PLL4P 0x00008F82
#define CLK_SDMMC3_HSI 0x00008F83
#define CLK_SDMMC3_DISABLED 0x00008F87
#define CLK_ETH_PLL4P 0x00008FC0
#define CLK_ETH_PLL3Q 0x00008FC1
#define CLK_ETH_DISABLED 0x00008FC3
#define CLK_QSPI_ACLK 0x00009000
#define CLK_QSPI_PLL3R 0x00009001
#define CLK_QSPI_PLL4P 0x00009002
#define CLK_QSPI_CKPER 0x00009003
#define CLK_FMC_ACLK 0x00009040
#define CLK_FMC_PLL3R 0x00009041
#define CLK_FMC_PLL4P 0x00009042
#define CLK_FMC_CKPER 0x00009043
#define CLK_FDCAN_HSE 0x000090C0
#define CLK_FDCAN_PLL3Q 0x000090C1
#define CLK_FDCAN_PLL4Q 0x000090C2
#define CLK_FDCAN_PLL4R 0x000090C3
#define CLK_SPDIF_PLL4P 0x00009140
#define CLK_SPDIF_PLL3Q 0x00009141
#define CLK_SPDIF_HSI 0x00009142
#define CLK_SPDIF_DISABLED 0x00009143
#define CLK_CEC_LSE 0x00009180
#define CLK_CEC_LSI 0x00009181
#define CLK_CEC_CSI_DIV122 0x00009182
#define CLK_CEC_DISABLED 0x00009183
#define CLK_USBPHY_HSE 0x000091C0
#define CLK_USBPHY_PLL4R 0x000091C1
#define CLK_USBPHY_HSE_DIV2 0x000091C2
#define CLK_USBPHY_DISABLED 0x000091C3
#define CLK_USBO_PLL4R 0x800091C0
#define CLK_USBO_USBPHY 0x800091C1
#define CLK_RNG1_CSI 0x00000CC0
#define CLK_RNG1_PLL4R 0x00000CC1
#define CLK_RNG1_LSE 0x00000CC2
#define CLK_RNG1_LSI 0x00000CC3
#define CLK_RNG2_CSI 0x00009200
#define CLK_RNG2_PLL4R 0x00009201
#define CLK_RNG2_LSE 0x00009202
#define CLK_RNG2_LSI 0x00009203
#define CLK_CKPER_HSI 0x00000D00
#define CLK_CKPER_CSI 0x00000D01
#define CLK_CKPER_HSE 0x00000D02
#define CLK_CKPER_DISABLED 0x00000D03
#define CLK_STGEN_HSI 0x00000D40
#define CLK_STGEN_HSE 0x00000D41
#define CLK_STGEN_DISABLED 0x00000D43
#define CLK_DSI_DSIPLL 0x00009240
#define CLK_DSI_PLL4P 0x00009241
#define CLK_ADC_PLL4R 0x00009280
#define CLK_ADC_CKPER 0x00009281
#define CLK_ADC_PLL3Q 0x00009282
#define CLK_ADC_DISABLED 0x00009283
#define CLK_LPTIM45_PCLK3 0x000092C0
#define CLK_LPTIM45_PLL4P 0x000092C1
#define CLK_LPTIM45_PLL3Q 0x000092C2
#define CLK_LPTIM45_LSE 0x000092C3
#define CLK_LPTIM45_LSI 0x000092C4
#define CLK_LPTIM45_CKPER 0x000092C5
#define CLK_LPTIM45_DISABLED 0x000092C7
#define CLK_LPTIM23_PCLK3 0x00009300
#define CLK_LPTIM23_PLL4Q 0x00009301
#define CLK_LPTIM23_CKPER 0x00009302
#define CLK_LPTIM23_LSE 0x00009303
#define CLK_LPTIM23_LSI 0x00009304
#define CLK_LPTIM23_DISABLED 0x00009307
#define CLK_LPTIM1_PCLK1 0x00009340
#define CLK_LPTIM1_PLL4P 0x00009341
#define CLK_LPTIM1_PLL3Q 0x00009342
#define CLK_LPTIM1_LSE 0x00009343
#define CLK_LPTIM1_LSI 0x00009344
#define CLK_LPTIM1_CKPER 0x00009345
#define CLK_LPTIM1_DISABLED 0x00009347
/* define for st,pll /csg */
#define SSCG_MODE_CENTER_SPREAD 0
#define SSCG_MODE_DOWN_SPREAD 1
/* define for st,drive */
#define LSEDRV_LOWEST 0
#define LSEDRV_MEDIUM_LOW 1
#define LSEDRV_MEDIUM_HIGH 2
#define LSEDRV_HIGHEST 3
#endif #endif

230
include/dt-bindings/clock/stm32mp13-clks.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_
#define _DT_BINDINGS_STM32MP13_CLKS_H_
/* OSCILLATOR clocks */
#define CK_HSE 0
#define CK_CSI 1
#define CK_LSI 2
#define CK_LSE 3
#define CK_HSI 4
#define CK_HSE_DIV2 5
/* PLL */
#define PLL1 6
#define PLL2 7
#define PLL3 8
#define PLL4 9
/* ODF */
#define PLL1_P 10
#define PLL1_Q 11
#define PLL1_R 12
#define PLL2_P 13
#define PLL2_Q 14
#define PLL2_R 15
#define PLL3_P 16
#define PLL3_Q 17
#define PLL3_R 18
#define PLL4_P 19
#define PLL4_Q 20
#define PLL4_R 21
#define PCLK1 22
#define PCLK2 23
#define PCLK3 24
#define PCLK4 25
#define PCLK5 26
#define PCLK6 27
/* SYSTEM CLOCK */
#define CK_PER 28
#define CK_MPU 29
#define CK_AXI 30
#define CK_MLAHB 31
/* BASE TIMER */
#define CK_TIMG1 32
#define CK_TIMG2 33
#define CK_TIMG3 34
/* AUX */
#define RTC 35
/* TRACE & DEBUG clocks */
#define CK_DBG 36
#define CK_TRACE 37
/* MCO clocks */
#define CK_MCO1 38
#define CK_MCO2 39
/* IP clocks */
#define SYSCFG 40
#define VREF 41
#define TMPSENS 42
#define PMBCTRL 43
#define HDP 44
#define IWDG2 45
#define STGENRO 46
#define USART1 47
#define RTCAPB 48
#define TZC 49
#define TZPC 50
#define IWDG1 51
#define BSEC 52
#define DMA1 53
#define DMA2 54
#define DMAMUX1 55
#define DMAMUX2 56
#define GPIOA 57
#define GPIOB 58
#define GPIOC 59
#define GPIOD 60
#define GPIOE 61
#define GPIOF 62
#define GPIOG 63
#define GPIOH 64
#define GPIOI 65
#define CRYP1 66
#define HASH1 67
#define BKPSRAM 68
#define MDMA 69
#define CRC1 70
#define USBH 71
#define DMA3 72
#define TSC 73
#define PKA 74
#define AXIMC 75
#define MCE 76
#define ETH1TX 77
#define ETH2TX 78
#define ETH1RX 79
#define ETH2RX 80
#define ETH1MAC 81
#define ETH2MAC 82
#define ETH1STP 83
#define ETH2STP 84
/* IP clocks with parents */
#define SDMMC1_K 85
#define SDMMC2_K 86
#define ADC1_K 87
#define ADC2_K 88
#define FMC_K 89
#define QSPI_K 90
#define RNG1_K 91
#define USBPHY_K 92
#define STGEN_K 93
#define SPDIF_K 94
#define SPI1_K 95
#define SPI2_K 96
#define SPI3_K 97
#define SPI4_K 98
#define SPI5_K 99
#define I2C1_K 100
#define I2C2_K 101
#define I2C3_K 102
#define I2C4_K 103
#define I2C5_K 104
#define TIM2_K 105
#define TIM3_K 106
#define TIM4_K 107
#define TIM5_K 108
#define TIM6_K 109
#define TIM7_K 110
#define TIM12_K 111
#define TIM13_K 112
#define TIM14_K 113
#define TIM1_K 114
#define TIM8_K 115
#define TIM15_K 116
#define TIM16_K 117
#define TIM17_K 118
#define LPTIM1_K 119
#define LPTIM2_K 120
#define LPTIM3_K 121
#define LPTIM4_K 122
#define LPTIM5_K 123
#define USART1_K 124
#define USART2_K 125
#define USART3_K 126
#define UART4_K 127
#define UART5_K 128
#define USART6_K 129
#define UART7_K 130
#define UART8_K 131
#define DFSDM_K 132
#define FDCAN_K 133
#define SAI1_K 134
#define SAI2_K 135
#define ADFSDM_K 136
#define USBO_K 137
#define LTDC_PX 138
#define ETH1CK_K 139
#define ETH1PTP_K 140
#define ETH2CK_K 141
#define ETH2PTP_K 142
#define DCMIPP_K 143
#define SAES_K 144
#define DTS_K 145
/* DDR */
#define DDRC1 146
#define DDRC1LP 147
#define DDRC2 148
#define DDRC2LP 149
#define DDRPHYC 150
#define DDRPHYCLP 151
#define DDRCAPB 152
#define DDRCAPBLP 153
#define AXIDCG 154
#define DDRPHYCAPB 155
#define DDRPHYCAPBLP 156
#define DDRPERFM 157
#define ADC1 158
#define ADC2 159
#define SAI1 160
#define SAI2 161
#define STM32MP1_LAST_CLK 162
/* SCMI clock identifiers */
#define CK_SCMI0_HSE 0
#define CK_SCMI0_HSI 1
#define CK_SCMI0_CSI 2
#define CK_SCMI0_LSE 3
#define CK_SCMI0_LSI 4
#define CK_SCMI0_HSE_DIV2 5
#define CK_SCMI0_PLL2_Q 6
#define CK_SCMI0_PLL2_R 7
#define CK_SCMI0_PLL3_P 8
#define CK_SCMI0_PLL3_Q 9
#define CK_SCMI0_PLL3_R 10
#define CK_SCMI0_PLL4_P 11
#define CK_SCMI0_PLL4_Q 12
#define CK_SCMI0_PLL4_R 13
#define CK_SCMI0_MPU 14
#define CK_SCMI0_AXI 15
#define CK_SCMI0_MLAHB 16
#define CK_SCMI0_CKPER 17
#define CK_SCMI0_PCLK1 18
#define CK_SCMI0_PCLK2 19
#define CK_SCMI0_PCLK3 20
#define CK_SCMI0_PCLK4 21
#define CK_SCMI0_PCLK5 22
#define CK_SCMI0_PCLK6 23
#define CK_SCMI0_CKTIMG1 24
#define CK_SCMI0_CKTIMG2 25
#define CK_SCMI0_CKTIMG3 26
#define CK_SCMI0_RTC 27
#define CK_SCMI0_RTCAPB 28
#define CK_SCMI0_BSEC 29
#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */

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/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
#ifndef _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_
#define _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_
#define CMD_DIV 0
#define CMD_MUX 1
#define CMD_CLK 2
#define CMD_RESERVED1 3
#define CMD_SHIFT 26
#define CMD_MASK 0xFC000000
#define CMD_DATA_MASK 0x03FFFFFF
#define DIV_ID_SHIFT 8
#define DIV_ID_MASK 0x0000FF00
#define DIV_DIVN_SHIFT 0
#define DIV_DIVN_MASK 0x000000FF
#define MUX_ID_SHIFT 4
#define MUX_ID_MASK 0x00000FF0
#define MUX_SEL_SHIFT 0
#define MUX_SEL_MASK 0x0000000F
#define CLK_ID_MASK GENMASK_32(19, 11)
#define CLK_ID_SHIFT 11
#define CLK_ON_MASK 0x00000400
#define CLK_ON_SHIFT 10
#define CLK_DIV_MASK GENMASK_32(9, 4)
#define CLK_DIV_SHIFT 4
#define CLK_SEL_MASK GENMASK_32(3, 0)
#define CLK_SEL_SHIFT 0
#define DIV_PLL1DIVP 0
#define DIV_PLL2DIVP 1
#define DIV_PLL2DIVQ 2
#define DIV_PLL2DIVR 3
#define DIV_PLL3DIVP 4
#define DIV_PLL3DIVQ 5
#define DIV_PLL3DIVR 6
#define DIV_PLL4DIVP 7
#define DIV_PLL4DIVQ 8
#define DIV_PLL4DIVR 9
#define DIV_MPU 10
#define DIV_AXI 11
#define DIV_MLAHB 12
#define DIV_APB1 13
#define DIV_APB2 14
#define DIV_APB3 15
#define DIV_APB4 16
#define DIV_APB5 17
#define DIV_APB6 18
#define DIV_RTC 19
#define DIV_MCO1 20
#define DIV_MCO2 21
#define DIV_HSI 22
#define DIV_TRACE 23
#define DIV_ETH1PTP 24
#define DIV_ETH2PTP 25
#define DIV_MAX 26
#define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\
((div_id) << DIV_ID_SHIFT |\
(div)))
#define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\
((mux_id) << MUX_ID_SHIFT |\
(sel)))
/* MCO output is enable */
#define MCO_SRC(mco_id, sel) ((CMD_CLK << CMD_SHIFT) |\
(((mco_id) << CLK_ID_SHIFT) |\
(sel)) | CLK_ON_MASK)
#define MCO_DISABLED(mco_id) ((CMD_CLK << CMD_SHIFT) |\
((mco_id) << CLK_ID_SHIFT))
/* CLK output is enable */
#define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\
(((clk_id) << CLK_ID_SHIFT) |\
(sel)) | CLK_ON_MASK)
#define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\
((clk_id) << CLK_ID_SHIFT))
#define MUX_MPU 0
#define MUX_AXI 1
#define MUX_MLAHB 2
#define MUX_PLL12 3
#define MUX_PLL3 4
#define MUX_PLL4 5
#define MUX_RTC 6
#define MUX_MCO1 7
#define MUX_MCO2 8
#define MUX_CKPER 9
#define MUX_KERNEL_BEGIN 10
#define MUX_ADC1 10
#define MUX_ADC2 11
#define MUX_DCMIPP 12
#define MUX_ETH1 13
#define MUX_ETH2 14
#define MUX_FDCAN 15
#define MUX_FMC 16
#define MUX_I2C12 17
#define MUX_I2C3 18
#define MUX_I2C4 19
#define MUX_I2C5 20
#define MUX_LPTIM1 21
#define MUX_LPTIM2 22
#define MUX_LPTIM3 23
#define MUX_LPTIM45 24
#define MUX_QSPI 25
#define MUX_RNG1 26
#define MUX_SAES 27
#define MUX_SAI1 28
#define MUX_SAI2 29
#define MUX_SDMMC1 30
#define MUX_SDMMC2 31
#define MUX_SPDIF 32
#define MUX_SPI1 33
#define MUX_SPI23 34
#define MUX_SPI4 35
#define MUX_SPI5 36
#define MUX_STGEN 37
#define MUX_UART1 38
#define MUX_UART2 39
#define MUX_UART35 40
#define MUX_UART4 41
#define MUX_UART6 42
#define MUX_UART78 43
#define MUX_USBO 44
#define MUX_USBPHY 45
#define MUX_MAX 46
#define CLK_MPU_HSI CLKSRC(MUX_MPU, 0)
#define CLK_MPU_HSE CLKSRC(MUX_MPU, 1)
#define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2)
#define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3)
#define CLK_AXI_HSI CLKSRC(MUX_AXI, 0)
#define CLK_AXI_HSE CLKSRC(MUX_AXI, 1)
#define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2)
#define CLK_MLAHBS_HSI CLKSRC(MUX_MLAHB, 0)
#define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1)
#define CLK_MLAHBS_CSI CLKSRC(MUX_MLAHB, 2)
#define CLK_MLAHBS_PLL3 CLKSRC(MUX_MLAHB, 3)
#define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0)
#define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1)
#define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0)
#define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1)
#define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2)
#define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0)
#define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1)
#define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2)
#define CLK_RTC_DISABLED CLK_DISABLED(RTC)
#define CLK_RTC_LSE CLK_SRC(RTC, 1)
#define CLK_RTC_LSI CLK_SRC(RTC, 2)
#define CLK_RTC_HSE CLK_SRC(RTC, 3)
#define CLK_MCO1_HSI CLK_SRC(CK_MCO1, 0)
#define CLK_MCO1_HSE CLK_SRC(CK_MCO1, 1)
#define CLK_MCO1_CSI CLK_SRC(CK_MCO1, 2)
#define CLK_MCO1_LSI CLK_SRC(CK_MCO1, 3)
#define CLK_MCO1_LSE CLK_SRC(CK_MCO1, 4)
#define CLK_MCO1_DISABLED CLK_DISABLED(CK_MCO1)
#define CLK_MCO2_MPU CLK_SRC(CK_MCO2, 0)
#define CLK_MCO2_AXI CLK_SRC(CK_MCO2, 1)
#define CLK_MCO2_MLAHB CLK_SRC(CK_MCO2, 2)
#define CLK_MCO2_PLL4 CLK_SRC(CK_MCO2, 3)
#define CLK_MCO2_HSE CLK_SRC(CK_MCO2, 4)
#define CLK_MCO2_HSI CLK_SRC(CK_MCO2, 5)
#define CLK_MCO2_DISABLED CLK_DISABLED(CK_MCO2)
#define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0)
#define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1)
#define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2)
#define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3)
#define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0)
#define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1)
#define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2)
#define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3)
#define CLK_I2C3_PCLK6 CLKSRC(MUX_I2C3, 0)
#define CLK_I2C3_PLL4R CLKSRC(MUX_I2C3, 1)
#define CLK_I2C3_HSI CLKSRC(MUX_I2C3, 2)
#define CLK_I2C3_CSI CLKSRC(MUX_I2C3, 3)
#define CLK_I2C4_PCLK6 CLKSRC(MUX_I2C4, 0)
#define CLK_I2C4_PLL4R CLKSRC(MUX_I2C4, 1)
#define CLK_I2C4_HSI CLKSRC(MUX_I2C4, 2)
#define CLK_I2C4_CSI CLKSRC(MUX_I2C4, 3)
#define CLK_I2C5_PCLK6 CLKSRC(MUX_I2C5, 0)
#define CLK_I2C5_PLL4R CLKSRC(MUX_I2C5, 1)
#define CLK_I2C5_HSI CLKSRC(MUX_I2C5, 2)
#define CLK_I2C5_CSI CLKSRC(MUX_I2C5, 3)
#define CLK_SPI1_PLL4P CLKSRC(MUX_SPI1, 0)
#define CLK_SPI1_PLL3Q CLKSRC(MUX_SPI1, 1)
#define CLK_SPI1_I2SCKIN CLKSRC(MUX_SPI1, 2)
#define CLK_SPI1_CKPER CLKSRC(MUX_SPI1, 3)
#define CLK_SPI1_PLL3R CLKSRC(MUX_SPI1, 4)
#define CLK_SPI23_PLL4P CLKSRC(MUX_SPI23, 0)
#define CLK_SPI23_PLL3Q CLKSRC(MUX_SPI23, 1)
#define CLK_SPI23_I2SCKIN CLKSRC(MUX_SPI23, 2)
#define CLK_SPI23_CKPER CLKSRC(MUX_SPI23, 3)
#define CLK_SPI23_PLL3R CLKSRC(MUX_SPI23, 4)
#define CLK_SPI4_PCLK6 CLKSRC(MUX_SPI4, 0)
#define CLK_SPI4_PLL4Q CLKSRC(MUX_SPI4, 1)
#define CLK_SPI4_HSI CLKSRC(MUX_SPI4, 2)
#define CLK_SPI4_CSI CLKSRC(MUX_SPI4, 3)
#define CLK_SPI4_HSE CLKSRC(MUX_SPI4, 4)
#define CLK_SPI4_I2SCKIN CLKSRC(MUX_SPI4, 5)
#define CLK_SPI5_PCLK6 CLKSRC(MUX_SPI5, 0)
#define CLK_SPI5_PLL4Q CLKSRC(MUX_SPI5, 1)
#define CLK_SPI5_HSI CLKSRC(MUX_SPI5, 2)
#define CLK_SPI5_CSI CLKSRC(MUX_SPI5, 3)
#define CLK_SPI5_HSE CLKSRC(MUX_SPI5, 4)
#define CLK_UART1_PCLK6 CLKSRC(MUX_UART1, 0)
#define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1)
#define CLK_UART1_HSI CLKSRC(MUX_UART1, 2)
#define CLK_UART1_CSI CLKSRC(MUX_UART1, 3)
#define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4)
#define CLK_UART1_HSE CLKSRC(MUX_UART1, 5)
#define CLK_UART2_PCLK6 CLKSRC(MUX_UART2, 0)
#define CLK_UART2_PLL3Q CLKSRC(MUX_UART2, 1)
#define CLK_UART2_HSI CLKSRC(MUX_UART2, 2)
#define CLK_UART2_CSI CLKSRC(MUX_UART2, 3)
#define CLK_UART2_PLL4Q CLKSRC(MUX_UART2, 4)
#define CLK_UART2_HSE CLKSRC(MUX_UART2, 5)
#define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0)
#define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1)
#define CLK_UART35_HSI CLKSRC(MUX_UART35, 2)
#define CLK_UART35_CSI CLKSRC(MUX_UART35, 3)
#define CLK_UART35_HSE CLKSRC(MUX_UART35, 4)
#define CLK_UART4_PCLK1 CLKSRC(MUX_UART4, 0)
#define CLK_UART4_PLL4Q CLKSRC(MUX_UART4, 1)
#define CLK_UART4_HSI CLKSRC(MUX_UART4, 2)
#define CLK_UART4_CSI CLKSRC(MUX_UART4, 3)
#define CLK_UART4_HSE CLKSRC(MUX_UART4, 4)
#define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0)
#define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1)
#define CLK_UART6_HSI CLKSRC(MUX_UART6, 2)
#define CLK_UART6_CSI CLKSRC(MUX_UART6, 3)
#define CLK_UART6_HSE CLKSRC(MUX_UART6, 4)
#define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0)
#define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1)
#define CLK_UART78_HSI CLKSRC(MUX_UART78, 2)
#define CLK_UART78_CSI CLKSRC(MUX_UART78, 3)
#define CLK_UART78_HSE CLKSRC(MUX_UART78, 4)
#define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0)
#define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1)
#define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2)
#define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3)
#define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4)
#define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5)
#define CLK_LPTIM2_PCLK3 CLKSRC(MUX_LPTIM2, 0)
#define CLK_LPTIM2_PLL4Q CLKSRC(MUX_LPTIM2, 1)
#define CLK_LPTIM2_CKPER CLKSRC(MUX_LPTIM2, 2)
#define CLK_LPTIM2_LSE CLKSRC(MUX_LPTIM2, 3)
#define CLK_LPTIM2_LSI CLKSRC(MUX_LPTIM2, 4)
#define CLK_LPTIM3_PCLK3 CLKSRC(MUX_LPTIM3, 0)
#define CLK_LPTIM3_PLL4Q CLKSRC(MUX_LPTIM3, 1)
#define CLK_LPTIM3_CKPER CLKSRC(MUX_LPTIM3, 2)
#define CLK_LPTIM3_LSE CLKSRC(MUX_LPTIM3, 3)
#define CLK_LPTIM3_LSI CLKSRC(MUX_LPTIM3, 4)
#define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0)
#define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1)
#define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2)
#define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3)
#define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4)
#define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5)
#define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0)
#define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1)
#define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2)
#define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3)
#define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4)
#define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0)
#define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1)
#define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2)
#define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3)
#define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4)
#define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5)
#define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0)
#define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1)
#define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2)
#define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3)
#define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0)
#define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1)
#define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2)
#define CLK_ADC1_PLL4R CLKSRC(MUX_ADC1, 0)
#define CLK_ADC1_CKPER CLKSRC(MUX_ADC1, 1)
#define CLK_ADC1_PLL3Q CLKSRC(MUX_ADC1, 2)
#define CLK_ADC2_PLL4R CLKSRC(MUX_ADC2, 0)
#define CLK_ADC2_CKPER CLKSRC(MUX_ADC2, 1)
#define CLK_ADC2_PLL3Q CLKSRC(MUX_ADC2, 2)
#define CLK_SDMMC1_HCLK6 CLKSRC(MUX_SDMMC1, 0)
#define CLK_SDMMC1_PLL3R CLKSRC(MUX_SDMMC1, 1)
#define CLK_SDMMC1_PLL4P CLKSRC(MUX_SDMMC1, 2)
#define CLK_SDMMC1_HSI CLKSRC(MUX_SDMMC1, 3)
#define CLK_SDMMC2_HCLK6 CLKSRC(MUX_SDMMC2, 0)
#define CLK_SDMMC2_PLL3R CLKSRC(MUX_SDMMC2, 1)
#define CLK_SDMMC2_PLL4P CLKSRC(MUX_SDMMC2, 2)
#define CLK_SDMMC2_HSI CLKSRC(MUX_SDMMC2, 3)
#define CLK_ETH1_PLL4P CLKSRC(MUX_ETH1, 0)
#define CLK_ETH1_PLL3Q CLKSRC(MUX_ETH1, 1)
#define CLK_ETH2_PLL4P CLKSRC(MUX_ETH2, 0)
#define CLK_ETH2_PLL3Q CLKSRC(MUX_ETH2, 1)
#define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0)
#define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1)
#define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2)
#define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0)
#define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1)
#define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0)
#define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1)
#define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2)
#define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3)
#define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0)
#define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1)
#define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2)
#define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3)
#define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0)
#define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1)
/* WARNING: POSITION 2 OF RNG1 MUX IS RESERVED */
#define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3)
#define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0)
#define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1)
#define CLK_DCMIPP_ACLK CLKSRC(MUX_DCMIPP, 0)
#define CLK_DCMIPP_PLL2Q CLKSRC(MUX_DCMIPP, 1)
#define CLK_DCMIPP_PLL4P CLKSRC(MUX_DCMIPP, 2)
#define CLK_DCMIPP_CKPER CLKSRC(MUX_DCMIPP, 3)
#define CLK_SAES_AXI CLKSRC(MUX_SAES, 0)
#define CLK_SAES_CKPER CLKSRC(MUX_SAES, 1)
#define CLK_SAES_PLL4R CLKSRC(MUX_SAES, 2)
#define CLK_SAES_LSI CLKSRC(MUX_SAES, 3)
/* PLL output is enable when x=1, with x=p,q or r */
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
/* define for st,pll /csg */
#define SSCG_MODE_CENTER_SPREAD 0
#define SSCG_MODE_DOWN_SPREAD 1
/* define for st,drive */
#define LSEDRV_LOWEST 0
#define LSEDRV_MEDIUM_LOW 1
#define LSEDRV_MEDIUM_HIGH 2
#define LSEDRV_HIGHEST 3
#endif /* _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ */

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/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
#define _DT_BINDINGS_STM32MP1_CLKS_H_
/* OSCILLATOR clocks */
#define CK_HSE 0
#define CK_CSI 1
#define CK_LSI 2
#define CK_LSE 3
#define CK_HSI 4
#define CK_HSE_DIV2 5
/* Bus clocks */
#define TIM2 6
#define TIM3 7
#define TIM4 8
#define TIM5 9
#define TIM6 10
#define TIM7 11
#define TIM12 12
#define TIM13 13
#define TIM14 14
#define LPTIM1 15
#define SPI2 16
#define SPI3 17
#define USART2 18
#define USART3 19
#define UART4 20
#define UART5 21
#define UART7 22
#define UART8 23
#define I2C1 24
#define I2C2 25
#define I2C3 26
#define I2C5 27
#define SPDIF 28
#define CEC 29
#define DAC12 30
#define MDIO 31
#define TIM1 32
#define TIM8 33
#define TIM15 34
#define TIM16 35
#define TIM17 36
#define SPI1 37
#define SPI4 38
#define SPI5 39
#define USART6 40
#define SAI1 41
#define SAI2 42
#define SAI3 43
#define DFSDM 44
#define FDCAN 45
#define LPTIM2 46
#define LPTIM3 47
#define LPTIM4 48
#define LPTIM5 49
#define SAI4 50
#define SYSCFG 51
#define VREF 52
#define TMPSENS 53
#define PMBCTRL 54
#define HDP 55
#define LTDC 56
#define DSI 57
#define IWDG2 58
#define USBPHY 59
#define STGENRO 60
#define SPI6 61
#define I2C4 62
#define I2C6 63
#define USART1 64
#define RTCAPB 65
#define TZC1 66
#define TZPC 67
#define IWDG1 68
#define BSEC 69
#define STGEN 70
#define DMA1 71
#define DMA2 72
#define DMAMUX 73
#define ADC12 74
#define USBO 75
#define SDMMC3 76
#define DCMI 77
#define CRYP2 78
#define HASH2 79
#define RNG2 80
#define CRC2 81
#define HSEM 82
#define IPCC 83
#define GPIOA 84
#define GPIOB 85
#define GPIOC 86
#define GPIOD 87
#define GPIOE 88
#define GPIOF 89
#define GPIOG 90
#define GPIOH 91
#define GPIOI 92
#define GPIOJ 93
#define GPIOK 94
#define GPIOZ 95
#define CRYP1 96
#define HASH1 97
#define RNG1 98
#define BKPSRAM 99
#define MDMA 100
#define GPU 101
#define ETHCK 102
#define ETHTX 103
#define ETHRX 104
#define ETHMAC 105
#define FMC 106
#define QSPI 107
#define SDMMC1 108
#define SDMMC2 109
#define CRC1 110
#define USBH 111
#define ETHSTP 112
#define TZC2 113
/* Kernel clocks */
#define SDMMC1_K 118
#define SDMMC2_K 119
#define SDMMC3_K 120
#define FMC_K 121
#define QSPI_K 122
#define ETHCK_K 123
#define RNG1_K 124
#define RNG2_K 125
#define GPU_K 126
#define USBPHY_K 127
#define STGEN_K 128
#define SPDIF_K 129
#define SPI1_K 130
#define SPI2_K 131
#define SPI3_K 132
#define SPI4_K 133
#define SPI5_K 134
#define SPI6_K 135
#define CEC_K 136
#define I2C1_K 137
#define I2C2_K 138
#define I2C3_K 139
#define I2C4_K 140
#define I2C5_K 141
#define I2C6_K 142
#define LPTIM1_K 143
#define LPTIM2_K 144
#define LPTIM3_K 145
#define LPTIM4_K 146
#define LPTIM5_K 147
#define USART1_K 148
#define USART2_K 149
#define USART3_K 150
#define UART4_K 151
#define UART5_K 152
#define USART6_K 153
#define UART7_K 154
#define UART8_K 155
#define DFSDM_K 156
#define FDCAN_K 157
#define SAI1_K 158
#define SAI2_K 159
#define SAI3_K 160
#define SAI4_K 161
#define ADC12_K 162
#define DSI_K 163
#define DSI_PX 164
#define ADFSDM_K 165
#define USBO_K 166
#define LTDC_PX 167
#define DAC12_K 168
#define ETHPTP_K 169
/* PLL */
#define PLL1 176
#define PLL2 177
#define PLL3 178
#define PLL4 179
/* ODF */
#define PLL1_P 180
#define PLL1_Q 181
#define PLL1_R 182
#define PLL2_P 183
#define PLL2_Q 184
#define PLL2_R 185
#define PLL3_P 186
#define PLL3_Q 187
#define PLL3_R 188
#define PLL4_P 189
#define PLL4_Q 190
#define PLL4_R 191
/* AUX */
#define RTC 192
/* MCLK */
#define CK_PER 193
#define CK_MPU 194
#define CK_AXI 195
#define CK_MCU 196
/* Time base */
#define TIM2_K 197
#define TIM3_K 198
#define TIM4_K 199
#define TIM5_K 200
#define TIM6_K 201
#define TIM7_K 202
#define TIM12_K 203
#define TIM13_K 204
#define TIM14_K 205
#define TIM1_K 206
#define TIM8_K 207
#define TIM15_K 208
#define TIM16_K 209
#define TIM17_K 210
/* MCO clocks */
#define CK_MCO1 211
#define CK_MCO2 212
/* TRACE & DEBUG clocks */
#define CK_DBG 214
#define CK_TRACE 215
/* DDR */
#define DDRC1 220
#define DDRC1LP 221
#define DDRC2 222
#define DDRC2LP 223
#define DDRPHYC 224
#define DDRPHYCLP 225
#define DDRCAPB 226
#define DDRCAPBLP 227
#define AXIDCG 228
#define DDRPHYCAPB 229
#define DDRPHYCAPBLP 230
#define DDRPERFM 231
#define STM32MP1_LAST_CLK 232
/* SCMI clock identifiers */
#define CK_SCMI0_HSE 0
#define CK_SCMI0_HSI 1
#define CK_SCMI0_CSI 2
#define CK_SCMI0_LSE 3
#define CK_SCMI0_LSI 4
#define CK_SCMI0_PLL2_Q 5
#define CK_SCMI0_PLL2_R 6
#define CK_SCMI0_MPU 7
#define CK_SCMI0_AXI 8
#define CK_SCMI0_BSEC 9
#define CK_SCMI0_CRYP1 10
#define CK_SCMI0_GPIOZ 11
#define CK_SCMI0_HASH1 12
#define CK_SCMI0_I2C4 13
#define CK_SCMI0_I2C6 14
#define CK_SCMI0_IWDG1 15
#define CK_SCMI0_RNG1 16
#define CK_SCMI0_RTC 17
#define CK_SCMI0_RTCAPB 18
#define CK_SCMI0_SPI6 19
#define CK_SCMI0_USART1 20
#define CK_SCMI1_PLL3_Q 0
#define CK_SCMI1_PLL3_R 1
#define CK_SCMI1_MCU 2
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */

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/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
* Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved
*/
#ifndef _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_
#define _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_
/* PLL output is enable when x=1, with x=p,q or r */
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
/* st,clksrc: mandatory clock source */
#define CLK_MPU_HSI 0x00000200
#define CLK_MPU_HSE 0x00000201
#define CLK_MPU_PLL1P 0x00000202
#define CLK_MPU_PLL1P_DIV 0x00000203
#define CLK_AXI_HSI 0x00000240
#define CLK_AXI_HSE 0x00000241
#define CLK_AXI_PLL2P 0x00000242
#define CLK_MCU_HSI 0x00000480
#define CLK_MCU_HSE 0x00000481
#define CLK_MCU_CSI 0x00000482
#define CLK_MCU_PLL3P 0x00000483
#define CLK_PLL12_HSI 0x00000280
#define CLK_PLL12_HSE 0x00000281
#define CLK_PLL3_HSI 0x00008200
#define CLK_PLL3_HSE 0x00008201
#define CLK_PLL3_CSI 0x00008202
#define CLK_PLL4_HSI 0x00008240
#define CLK_PLL4_HSE 0x00008241
#define CLK_PLL4_CSI 0x00008242
#define CLK_PLL4_I2SCKIN 0x00008243
#define CLK_RTC_DISABLED 0x00001400
#define CLK_RTC_LSE 0x00001401
#define CLK_RTC_LSI 0x00001402
#define CLK_RTC_HSE 0x00001403
#define CLK_MCO1_HSI 0x00008000
#define CLK_MCO1_HSE 0x00008001
#define CLK_MCO1_CSI 0x00008002
#define CLK_MCO1_LSI 0x00008003
#define CLK_MCO1_LSE 0x00008004
#define CLK_MCO1_DISABLED 0x0000800F
#define CLK_MCO2_MPU 0x00008040
#define CLK_MCO2_AXI 0x00008041
#define CLK_MCO2_MCU 0x00008042
#define CLK_MCO2_PLL4P 0x00008043
#define CLK_MCO2_HSE 0x00008044
#define CLK_MCO2_HSI 0x00008045
#define CLK_MCO2_DISABLED 0x0000804F
/* st,pkcs: peripheral kernel clock source */
#define CLK_I2C12_PCLK1 0x00008C00
#define CLK_I2C12_PLL4R 0x00008C01
#define CLK_I2C12_HSI 0x00008C02
#define CLK_I2C12_CSI 0x00008C03
#define CLK_I2C12_DISABLED 0x00008C07
#define CLK_I2C35_PCLK1 0x00008C40
#define CLK_I2C35_PLL4R 0x00008C41
#define CLK_I2C35_HSI 0x00008C42
#define CLK_I2C35_CSI 0x00008C43
#define CLK_I2C35_DISABLED 0x00008C47
#define CLK_I2C46_PCLK5 0x00000C00
#define CLK_I2C46_PLL3Q 0x00000C01
#define CLK_I2C46_HSI 0x00000C02
#define CLK_I2C46_CSI 0x00000C03
#define CLK_I2C46_DISABLED 0x00000C07
#define CLK_SAI1_PLL4Q 0x00008C80
#define CLK_SAI1_PLL3Q 0x00008C81
#define CLK_SAI1_I2SCKIN 0x00008C82
#define CLK_SAI1_CKPER 0x00008C83
#define CLK_SAI1_PLL3R 0x00008C84
#define CLK_SAI1_DISABLED 0x00008C87
#define CLK_SAI2_PLL4Q 0x00008CC0
#define CLK_SAI2_PLL3Q 0x00008CC1
#define CLK_SAI2_I2SCKIN 0x00008CC2
#define CLK_SAI2_CKPER 0x00008CC3
#define CLK_SAI2_SPDIF 0x00008CC4
#define CLK_SAI2_PLL3R 0x00008CC5
#define CLK_SAI2_DISABLED 0x00008CC7
#define CLK_SAI3_PLL4Q 0x00008D00
#define CLK_SAI3_PLL3Q 0x00008D01
#define CLK_SAI3_I2SCKIN 0x00008D02
#define CLK_SAI3_CKPER 0x00008D03
#define CLK_SAI3_PLL3R 0x00008D04
#define CLK_SAI3_DISABLED 0x00008D07
#define CLK_SAI4_PLL4Q 0x00008D40
#define CLK_SAI4_PLL3Q 0x00008D41
#define CLK_SAI4_I2SCKIN 0x00008D42
#define CLK_SAI4_CKPER 0x00008D43
#define CLK_SAI4_PLL3R 0x00008D44
#define CLK_SAI4_DISABLED 0x00008D47
#define CLK_SPI2S1_PLL4P 0x00008D80
#define CLK_SPI2S1_PLL3Q 0x00008D81
#define CLK_SPI2S1_I2SCKIN 0x00008D82
#define CLK_SPI2S1_CKPER 0x00008D83
#define CLK_SPI2S1_PLL3R 0x00008D84
#define CLK_SPI2S1_DISABLED 0x00008D87
#define CLK_SPI2S23_PLL4P 0x00008DC0
#define CLK_SPI2S23_PLL3Q 0x00008DC1
#define CLK_SPI2S23_I2SCKIN 0x00008DC2
#define CLK_SPI2S23_CKPER 0x00008DC3
#define CLK_SPI2S23_PLL3R 0x00008DC4
#define CLK_SPI2S23_DISABLED 0x00008DC7
#define CLK_SPI45_PCLK2 0x00008E00
#define CLK_SPI45_PLL4Q 0x00008E01
#define CLK_SPI45_HSI 0x00008E02
#define CLK_SPI45_CSI 0x00008E03
#define CLK_SPI45_HSE 0x00008E04
#define CLK_SPI45_DISABLED 0x00008E07
#define CLK_SPI6_PCLK5 0x00000C40
#define CLK_SPI6_PLL4Q 0x00000C41
#define CLK_SPI6_HSI 0x00000C42
#define CLK_SPI6_CSI 0x00000C43
#define CLK_SPI6_HSE 0x00000C44
#define CLK_SPI6_PLL3Q 0x00000C45
#define CLK_SPI6_DISABLED 0x00000C47
#define CLK_UART6_PCLK2 0x00008E40
#define CLK_UART6_PLL4Q 0x00008E41
#define CLK_UART6_HSI 0x00008E42
#define CLK_UART6_CSI 0x00008E43
#define CLK_UART6_HSE 0x00008E44
#define CLK_UART6_DISABLED 0x00008E47
#define CLK_UART24_PCLK1 0x00008E80
#define CLK_UART24_PLL4Q 0x00008E81
#define CLK_UART24_HSI 0x00008E82
#define CLK_UART24_CSI 0x00008E83
#define CLK_UART24_HSE 0x00008E84
#define CLK_UART24_DISABLED 0x00008E87
#define CLK_UART35_PCLK1 0x00008EC0
#define CLK_UART35_PLL4Q 0x00008EC1
#define CLK_UART35_HSI 0x00008EC2
#define CLK_UART35_CSI 0x00008EC3
#define CLK_UART35_HSE 0x00008EC4
#define CLK_UART35_DISABLED 0x00008EC7
#define CLK_UART78_PCLK1 0x00008F00
#define CLK_UART78_PLL4Q 0x00008F01
#define CLK_UART78_HSI 0x00008F02
#define CLK_UART78_CSI 0x00008F03
#define CLK_UART78_HSE 0x00008F04
#define CLK_UART78_DISABLED 0x00008F07
#define CLK_UART1_PCLK5 0x00000C80
#define CLK_UART1_PLL3Q 0x00000C81
#define CLK_UART1_HSI 0x00000C82
#define CLK_UART1_CSI 0x00000C83
#define CLK_UART1_PLL4Q 0x00000C84
#define CLK_UART1_HSE 0x00000C85
#define CLK_UART1_DISABLED 0x00000C87
#define CLK_SDMMC12_HCLK6 0x00008F40
#define CLK_SDMMC12_PLL3R 0x00008F41
#define CLK_SDMMC12_PLL4P 0x00008F42
#define CLK_SDMMC12_HSI 0x00008F43
#define CLK_SDMMC12_DISABLED 0x00008F47
#define CLK_SDMMC3_HCLK2 0x00008F80
#define CLK_SDMMC3_PLL3R 0x00008F81
#define CLK_SDMMC3_PLL4P 0x00008F82
#define CLK_SDMMC3_HSI 0x00008F83
#define CLK_SDMMC3_DISABLED 0x00008F87
#define CLK_ETH_PLL4P 0x00008FC0
#define CLK_ETH_PLL3Q 0x00008FC1
#define CLK_ETH_DISABLED 0x00008FC3
#define CLK_QSPI_ACLK 0x00009000
#define CLK_QSPI_PLL3R 0x00009001
#define CLK_QSPI_PLL4P 0x00009002
#define CLK_QSPI_CKPER 0x00009003
#define CLK_FMC_ACLK 0x00009040
#define CLK_FMC_PLL3R 0x00009041
#define CLK_FMC_PLL4P 0x00009042
#define CLK_FMC_CKPER 0x00009043
#define CLK_FDCAN_HSE 0x000090C0
#define CLK_FDCAN_PLL3Q 0x000090C1
#define CLK_FDCAN_PLL4Q 0x000090C2
#define CLK_FDCAN_PLL4R 0x000090C3
#define CLK_SPDIF_PLL4P 0x00009140
#define CLK_SPDIF_PLL3Q 0x00009141
#define CLK_SPDIF_HSI 0x00009142
#define CLK_SPDIF_DISABLED 0x00009143
#define CLK_CEC_LSE 0x00009180
#define CLK_CEC_LSI 0x00009181
#define CLK_CEC_CSI_DIV122 0x00009182
#define CLK_CEC_DISABLED 0x00009183
#define CLK_USBPHY_HSE 0x000091C0
#define CLK_USBPHY_PLL4R 0x000091C1
#define CLK_USBPHY_HSE_DIV2 0x000091C2
#define CLK_USBPHY_DISABLED 0x000091C3
#define CLK_USBO_PLL4R 0x800091C0
#define CLK_USBO_USBPHY 0x800091C1
#define CLK_RNG1_CSI 0x00000CC0
#define CLK_RNG1_PLL4R 0x00000CC1
#define CLK_RNG1_LSE 0x00000CC2
#define CLK_RNG1_LSI 0x00000CC3
#define CLK_RNG2_CSI 0x00009200
#define CLK_RNG2_PLL4R 0x00009201
#define CLK_RNG2_LSE 0x00009202
#define CLK_RNG2_LSI 0x00009203
#define CLK_CKPER_HSI 0x00000D00
#define CLK_CKPER_CSI 0x00000D01
#define CLK_CKPER_HSE 0x00000D02
#define CLK_CKPER_DISABLED 0x00000D03
#define CLK_STGEN_HSI 0x00000D40
#define CLK_STGEN_HSE 0x00000D41
#define CLK_STGEN_DISABLED 0x00000D43
#define CLK_DSI_DSIPLL 0x00009240
#define CLK_DSI_PLL4P 0x00009241
#define CLK_ADC_PLL4R 0x00009280
#define CLK_ADC_CKPER 0x00009281
#define CLK_ADC_PLL3Q 0x00009282
#define CLK_ADC_DISABLED 0x00009283
#define CLK_LPTIM45_PCLK3 0x000092C0
#define CLK_LPTIM45_PLL4P 0x000092C1
#define CLK_LPTIM45_PLL3Q 0x000092C2
#define CLK_LPTIM45_LSE 0x000092C3
#define CLK_LPTIM45_LSI 0x000092C4
#define CLK_LPTIM45_CKPER 0x000092C5
#define CLK_LPTIM45_DISABLED 0x000092C7
#define CLK_LPTIM23_PCLK3 0x00009300
#define CLK_LPTIM23_PLL4Q 0x00009301
#define CLK_LPTIM23_CKPER 0x00009302
#define CLK_LPTIM23_LSE 0x00009303
#define CLK_LPTIM23_LSI 0x00009304
#define CLK_LPTIM23_DISABLED 0x00009307
#define CLK_LPTIM1_PCLK1 0x00009340
#define CLK_LPTIM1_PLL4P 0x00009341
#define CLK_LPTIM1_PLL3Q 0x00009342
#define CLK_LPTIM1_LSE 0x00009343
#define CLK_LPTIM1_LSI 0x00009344
#define CLK_LPTIM1_CKPER 0x00009345
#define CLK_LPTIM1_DISABLED 0x00009347
/* define for st,pll /csg */
#define SSCG_MODE_CENTER_SPREAD 0
#define SSCG_MODE_DOWN_SPREAD 1
/* define for st,drive */
#define LSEDRV_LOWEST 0
#define LSEDRV_MEDIUM_LOW 1
#define LSEDRV_MEDIUM_HIGH 2
#define LSEDRV_HIGHEST 3
#endif

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include/dt-bindings/reset/stm32mp1-resets.h
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/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/* /*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved * Copyright (C) 2020-2022, STMicroelectronics - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/ */
#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ #if STM32MP13
#define _DT_BINDINGS_STM32MP1_RESET_H_ #include "stm32mp13-resets.h"
#endif
#define LTDC_R 3072 #if STM32MP15
#define DSI_R 3076 #include "stm32mp15-resets.h"
#define DDRPERFM_R 3080 #endif
#define USBPHY_R 3088
#define SPI6_R 3136
#define I2C4_R 3138
#define I2C6_R 3139
#define USART1_R 3140
#define STGEN_R 3156
#define GPIOZ_R 3200
#define CRYP1_R 3204
#define HASH1_R 3205
#define RNG1_R 3206
#define AXIM_R 3216
#define GPU_R 3269
#define ETHMAC_R 3274
#define FMC_R 3276
#define QSPI_R 3278
#define SDMMC1_R 3280
#define SDMMC2_R 3281
#define CRC1_R 3284
#define USBH_R 3288
#define MDMA_R 3328
#define MCU_R 8225
#define TIM2_R 19456
#define TIM3_R 19457
#define TIM4_R 19458
#define TIM5_R 19459
#define TIM6_R 19460
#define TIM7_R 19461
#define TIM12_R 16462
#define TIM13_R 16463
#define TIM14_R 16464
#define LPTIM1_R 19465
#define SPI2_R 19467
#define SPI3_R 19468
#define USART2_R 19470
#define USART3_R 19471
#define UART4_R 19472
#define UART5_R 19473
#define UART7_R 19474
#define UART8_R 19475
#define I2C1_R 19477
#define I2C2_R 19478
#define I2C3_R 19479
#define I2C5_R 19480
#define SPDIF_R 19482
#define CEC_R 19483
#define DAC12_R 19485
#define MDIO_R 19847
#define TIM1_R 19520
#define TIM8_R 19521
#define TIM15_R 19522
#define TIM16_R 19523
#define TIM17_R 19524
#define SPI1_R 19528
#define SPI4_R 19529
#define SPI5_R 19530
#define USART6_R 19533
#define SAI1_R 19536
#define SAI2_R 19537
#define SAI3_R 19538
#define DFSDM_R 19540
#define FDCAN_R 19544
#define LPTIM2_R 19584
#define LPTIM3_R 19585
#define LPTIM4_R 19586
#define LPTIM5_R 19587
#define SAI4_R 19592
#define SYSCFG_R 19595
#define VREF_R 19597
#define TMPSENS_R 19600
#define PMBCTRL_R 19601
#define DMA1_R 19648
#define DMA2_R 19649
#define DMAMUX_R 19650
#define ADC12_R 19653
#define USBO_R 19656
#define SDMMC3_R 19664
#define CAMITF_R 19712
#define CRYP2_R 19716
#define HASH2_R 19717
#define RNG2_R 19718
#define CRC2_R 19719
#define HSEM_R 19723
#define MBOX_R 19724
#define GPIOA_R 19776
#define GPIOB_R 19777
#define GPIOC_R 19778
#define GPIOD_R 19779
#define GPIOE_R 19780
#define GPIOF_R 19781
#define GPIOG_R 19782
#define GPIOH_R 19783
#define GPIOI_R 19784
#define GPIOJ_R 19785
#define GPIOK_R 19786
/* SCMI reset domain identifiers */
#define RST_SCMI0_SPI6 0
#define RST_SCMI0_I2C4 1
#define RST_SCMI0_I2C6 2
#define RST_SCMI0_USART1 3
#define RST_SCMI0_STGEN 4
#define RST_SCMI0_GPIOZ 5
#define RST_SCMI0_CRYP1 6
#define RST_SCMI0_HASH1 7
#define RST_SCMI0_RNG1 8
#define RST_SCMI0_MDMA 9
#define RST_SCMI0_MCU 10
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */

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/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP13_RESET_H_
#define _DT_BINDINGS_STM32MP13_RESET_H_
#define TIM2_R 13568
#define TIM3_R 13569
#define TIM4_R 13570
#define TIM5_R 13571
#define TIM6_R 13572
#define TIM7_R 13573
#define LPTIM1_R 13577
#define SPI2_R 13579
#define SPI3_R 13580
#define USART3_R 13583
#define UART4_R 13584
#define UART5_R 13585
#define UART7_R 13586
#define UART8_R 13587
#define I2C1_R 13589
#define I2C2_R 13590
#define SPDIF_R 13594
#define TIM1_R 13632
#define TIM8_R 13633
#define SPI1_R 13640
#define USART6_R 13645
#define SAI1_R 13648
#define SAI2_R 13649
#define DFSDM_R 13652
#define FDCAN_R 13656
#define LPTIM2_R 13696
#define LPTIM3_R 13697
#define LPTIM4_R 13698
#define LPTIM5_R 13699
#define SYSCFG_R 13707
#define VREF_R 13709
#define DTS_R 13712
#define PMBCTRL_R 13713
#define LTDC_R 13760
#define DCMIPP_R 13761
#define DDRPERFM_R 13768
#define USBPHY_R 13776
#define STGEN_R 13844
#define USART1_R 13888
#define USART2_R 13889
#define SPI4_R 13890
#define SPI5_R 13891
#define I2C3_R 13892
#define I2C4_R 13893
#define I2C5_R 13894
#define TIM12_R 13895
#define TIM13_R 13896
#define TIM14_R 13897
#define TIM15_R 13898
#define TIM16_R 13899
#define TIM17_R 13900
#define DMA1_R 13952
#define DMA2_R 13953
#define DMAMUX1_R 13954
#define DMA3_R 13955
#define DMAMUX2_R 13956
#define ADC1_R 13957
#define ADC2_R 13958
#define USBO_R 13960
#define GPIOA_R 14080
#define GPIOB_R 14081
#define GPIOC_R 14082
#define GPIOD_R 14083
#define GPIOE_R 14084
#define GPIOF_R 14085
#define GPIOG_R 14086
#define GPIOH_R 14087
#define GPIOI_R 14088
#define TSC_R 14095
#define PKA_R 14146
#define SAES_R 14147
#define CRYP1_R 14148
#define HASH1_R 14149
#define RNG1_R 14150
#define AXIMC_R 14160
#define MDMA_R 14208
#define MCE_R 14209
#define ETH1MAC_R 14218
#define FMC_R 14220
#define QSPI_R 14222
#define SDMMC1_R 14224
#define SDMMC2_R 14225
#define CRC1_R 14228
#define USBH_R 14232
#define ETH2MAC_R 14238
#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */

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include/dt-bindings/reset/stm32mp15-resets.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#ifndef _DT_BINDINGS_STM32MP15_RESET_H_
#define _DT_BINDINGS_STM32MP15_RESET_H_
#define MCU_HOLD_BOOT_R 2144
#define LTDC_R 3072
#define DSI_R 3076
#define DDRPERFM_R 3080
#define USBPHY_R 3088
#define SPI6_R 3136
#define I2C4_R 3138
#define I2C6_R 3139
#define USART1_R 3140
#define STGEN_R 3156
#define GPIOZ_R 3200
#define CRYP1_R 3204
#define HASH1_R 3205
#define RNG1_R 3206
#define AXIM_R 3216
#define GPU_R 3269
#define ETHMAC_R 3274
#define FMC_R 3276
#define QSPI_R 3278
#define SDMMC1_R 3280
#define SDMMC2_R 3281
#define CRC1_R 3284
#define USBH_R 3288
#define MDMA_R 3328
#define MCU_R 8225
#define TIM2_R 19456
#define TIM3_R 19457
#define TIM4_R 19458
#define TIM5_R 19459
#define TIM6_R 19460
#define TIM7_R 19461
#define TIM12_R 16462
#define TIM13_R 16463
#define TIM14_R 16464
#define LPTIM1_R 19465
#define SPI2_R 19467
#define SPI3_R 19468
#define USART2_R 19470
#define USART3_R 19471
#define UART4_R 19472
#define UART5_R 19473
#define UART7_R 19474
#define UART8_R 19475
#define I2C1_R 19477
#define I2C2_R 19478
#define I2C3_R 19479
#define I2C5_R 19480
#define SPDIF_R 19482
#define CEC_R 19483
#define DAC12_R 19485
#define MDIO_R 19847
#define TIM1_R 19520
#define TIM8_R 19521
#define TIM15_R 19522
#define TIM16_R 19523
#define TIM17_R 19524
#define SPI1_R 19528
#define SPI4_R 19529
#define SPI5_R 19530
#define USART6_R 19533
#define SAI1_R 19536
#define SAI2_R 19537
#define SAI3_R 19538
#define DFSDM_R 19540
#define FDCAN_R 19544
#define LPTIM2_R 19584
#define LPTIM3_R 19585
#define LPTIM4_R 19586
#define LPTIM5_R 19587
#define SAI4_R 19592
#define SYSCFG_R 19595
#define VREF_R 19597
#define TMPSENS_R 19600
#define PMBCTRL_R 19601
#define DMA1_R 19648
#define DMA2_R 19649
#define DMAMUX_R 19650
#define ADC12_R 19653
#define USBO_R 19656
#define SDMMC3_R 19664
#define CAMITF_R 19712
#define CRYP2_R 19716
#define HASH2_R 19717
#define RNG2_R 19718
#define CRC2_R 19719
#define HSEM_R 19723
#define MBOX_R 19724
#define GPIOA_R 19776
#define GPIOB_R 19777
#define GPIOC_R 19778
#define GPIOD_R 19779
#define GPIOE_R 19780
#define GPIOF_R 19781
#define GPIOG_R 19782
#define GPIOH_R 19783
#define GPIOI_R 19784
#define GPIOJ_R 19785
#define GPIOK_R 19786
/* SCMI reset domain identifiers */
#define RST_SCMI0_SPI6 0
#define RST_SCMI0_I2C4 1
#define RST_SCMI0_I2C6 2
#define RST_SCMI0_USART1 3
#define RST_SCMI0_STGEN 4
#define RST_SCMI0_GPIOZ 5
#define RST_SCMI0_CRYP1 6
#define RST_SCMI0_HASH1 7
#define RST_SCMI0_RNG1 8
#define RST_SCMI0_MDMA 9
#define RST_SCMI0_MCU 10
#define RST_SCMI0_MCU_HOLD_BOOT 11
#endif /* _DT_BINDINGS_STM32MP15_RESET_H_ */