From e2a65959bc610a4928a77b78532fec349a9cacb4 Mon Sep 17 00:00:00 2001 From: Jimmy Huang Date: Fri, 4 Mar 2016 20:18:58 +0800 Subject: [PATCH 1/3] mt8173: Add #error directive to prevent RESET_TO_BL31 MT8173 platform code is incompatible with RESET_TO_BL31, add #error directive to prevent the case. We also move mt8173_def.h and plat_private.h to include directory, and remove some unnecessary code. Change-Id: I47b8d0a506820a4ea1fbe8c8fb0ec6c68d88feb5 Signed-off-by: Jimmy Huang --- plat/mediatek/mt8173/aarch64/platform_common.c | 2 +- plat/mediatek/mt8173/bl31_plat_setup.c | 2 -- .../mediatek/mt8173/{ => include}/mt8173_def.h | 17 ++++++++++------- .../mt8173/{ => include}/plat_private.h | 0 plat/mediatek/mt8173/include/platform_def.h | 18 ++++++++++++++++-- plat/mediatek/mt8173/platform.mk | 1 - 6 files changed, 27 insertions(+), 13 deletions(-) rename plat/mediatek/mt8173/{ => include}/mt8173_def.h (94%) rename plat/mediatek/mt8173/{ => include}/plat_private.h (100%) diff --git a/plat/mediatek/mt8173/aarch64/platform_common.c b/plat/mediatek/mt8173/aarch64/platform_common.c index b537f7b2a..23116f5da 100644 --- a/plat/mediatek/mt8173/aarch64/platform_common.c +++ b/plat/mediatek/mt8173/aarch64/platform_common.c @@ -44,7 +44,7 @@ static const int cci_map[] = { /* Table of regions to map using the MMU. */ const mmap_region_t plat_mmap[] = { /* for TF text, RO, RW */ - MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE + TZRAM2_SIZE, + MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE), MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index ec9514322..87837759b 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -146,8 +146,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, assert(from_bl2->h.type == PARAM_BL31); assert(from_bl2->h.version >= VERSION_1); - assert(((unsigned long)plat_params_from_bl2) == MT_BL31_PLAT_PARAM_VAL); - bl32_ep_info = *from_bl2->bl32_ep_info; bl33_ep_info = *from_bl2->bl33_ep_info; } diff --git a/plat/mediatek/mt8173/mt8173_def.h b/plat/mediatek/mt8173/include/mt8173_def.h similarity index 94% rename from plat/mediatek/mt8173/mt8173_def.h rename to plat/mediatek/mt8173/include/mt8173_def.h index ecf4cc635..71668c75e 100644 --- a/plat/mediatek/mt8173/mt8173_def.h +++ b/plat/mediatek/mt8173/include/mt8173_def.h @@ -28,22 +28,25 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __PLAT_DEF_H__ -#define __PLAT_DEF_H__ +#ifndef __MT8173_DEF_H__ +#define __MT8173_DEF_H__ + +#if RESET_TO_BL31 +#error "MT8173 is incompatible with RESET_TO_BL31!" +#endif #define MT8173_PRIMARY_CPU 0x0 -/* Special value used to verify platform parameters from BL2 to BL3-1 */ -#define MT_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL - +/* Register base address */ #define IO_PHYS (0x10000000) #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) +#define PERI_CON_BASE (IO_PHYS + 0x3000) #define GPIO_BASE (IO_PHYS + 0x5000) #define SPM_BASE (IO_PHYS + 0x6000) #define RGU_BASE (IO_PHYS + 0x7000) #define PMIC_WRAP_BASE (IO_PHYS + 0xD000) #define MCUCFG_BASE (IO_PHYS + 0x200000) -#define TRNG_base (IO_PHYS + 0x20F000) +#define TRNG_BASE (IO_PHYS + 0x20F000) #define MT_GIC_BASE (IO_PHYS + 0x220000) #define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) @@ -112,4 +115,4 @@ #define MT_IRQ_SEC_SGI_6 14 #define MT_IRQ_SEC_SGI_7 15 -#endif /* __PLAT_DEF_H__ */ +#endif /* __MT8173_DEF_H__ */ diff --git a/plat/mediatek/mt8173/plat_private.h b/plat/mediatek/mt8173/include/plat_private.h similarity index 100% rename from plat/mediatek/mt8173/plat_private.h rename to plat/mediatek/mt8173/include/plat_private.h diff --git a/plat/mediatek/mt8173/include/platform_def.h b/plat/mediatek/mt8173/include/platform_def.h index 0573bc5e8..dc5b000e5 100644 --- a/plat/mediatek/mt8173/include/platform_def.h +++ b/plat/mediatek/mt8173/include/platform_def.h @@ -70,7 +70,21 @@ /******************************************************************************* * Platform memory map related constants ******************************************************************************/ -/* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */ +/* + * MT8173 SRAM memory layout + * 0x100000 +-------------------+ + * | shared mem (4KB) | + * 0x101000 +-------------------+ + * | | + * | BL3-1 (124KB) | + * | | + * 0x120000 +-------------------+ + * | reserved (64KB) | + * 0x130000 +-------------------+ + */ +/* TF txet, ro, rw, xlat table, coherent memory ... etc. + * Size: release: 128KB, debug: 128KB + */ #define TZRAM_BASE (0x100000) #if DEBUG #define TZRAM_SIZE (0x20000) @@ -78,7 +92,7 @@ #define TZRAM_SIZE (0x20000) #endif -/* xlat_table , coherence ram, 64KB */ +/* Reserved: 64KB */ #define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE) #define TZRAM2_SIZE (0x10000) diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk index 30df32f2a..7f07c15be 100644 --- a/plat/mediatek/mt8173/platform.mk +++ b/plat/mediatek/mt8173/platform.mk @@ -32,7 +32,6 @@ MTK_PLAT := plat/mediatek MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ - -I${MTK_PLAT_SOC}/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/mtcmos/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ From 76d47fea7ec6a5d2049142dfcbea88cd175bd51e Mon Sep 17 00:00:00 2001 From: Jimmy Huang Date: Sat, 5 Mar 2016 00:53:25 +0800 Subject: [PATCH 2/3] mt8173: Remove gpio driver support We no longer need to control power signal via gpio during system off, thus remove gpio driver support from platform code. Change-Id: I6dfec129fa163330951f37b45b71ba5b90355c3b Signed-off-by: Jimmy Huang --- plat/mediatek/mt8173/drivers/gpio/gpio.c | 198 ----------------------- plat/mediatek/mt8173/drivers/gpio/gpio.h | 184 --------------------- plat/mediatek/mt8173/plat_pm.c | 2 - plat/mediatek/mt8173/platform.mk | 2 - 4 files changed, 386 deletions(-) delete mode 100644 plat/mediatek/mt8173/drivers/gpio/gpio.c delete mode 100644 plat/mediatek/mt8173/drivers/gpio/gpio.h diff --git a/plat/mediatek/mt8173/drivers/gpio/gpio.c b/plat/mediatek/mt8173/drivers/gpio/gpio.c deleted file mode 100644 index f19c9315a..000000000 --- a/plat/mediatek/mt8173/drivers/gpio/gpio.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include -#include "gpio.h" - -enum { - MAX_GPIO_REG_BITS = 16, -}; - -struct mt_gpio_obj { - struct gpio_regs *reg; -}; - -static struct mt_gpio_obj gpio_dat = { - .reg = (struct gpio_regs *)(GPIO_BASE), -}; - -static struct mt_gpio_obj *gpio_obj = &gpio_dat; - -struct mt_gpioext_obj { - struct gpioext_regs *reg; -}; - -static struct mt_gpioext_obj gpioext_dat = { - .reg = (struct gpioext_regs *)(GPIOEXT_BASE), -}; - -static struct mt_gpioext_obj *gpioext_obj = &gpioext_dat; - -static inline struct mt_gpio_obj *mt_get_gpio_obj(void) -{ - return gpio_obj; -} - -static inline struct mt_gpioext_obj *mt_get_gpioext_obj(void) -{ - return gpioext_obj; -} - -enum { - GPIO_PRO_DIR = 0, - GPIO_PRO_DOUT, - GPIO_PRO_DIN, - GPIO_PRO_PULLEN, - GPIO_PRO_PULLSEL, - GPIO_PRO_MODE, - GPIO_PRO_MAX, -}; - -static inline int32_t gpioext_write(uint16_t *addr, int64_t data) -{ - return pwrap_write((uint32_t)(uintptr_t)addr, data); -} - -static inline int32_t gpioext_set_bits(uint32_t bit, uint16_t *reg) -{ - return gpioext_write(reg, bit); -} - -static int32_t mt_set_gpio_chip(uint32_t pin, uint32_t property, uint32_t val) -{ - uint32_t pos = 0; - uint32_t bit = 0; - struct mt_gpio_obj *obj = mt_get_gpio_obj(); - uint16_t *reg; - uint32_t data = 0; - - if (!obj) - return -ERACCESS; - - if (pin >= GPIO_EXTEND_START) - return -ERINVAL; - - if (property >= GPIO_PRO_MAX) - return -ERINVAL; - - pos = pin / MAX_GPIO_REG_BITS; - bit = pin % MAX_GPIO_REG_BITS; - data = 1L << bit; - - switch (property) { - case GPIO_PRO_DIR: - if (val == GPIO_DIR_IN) - reg = &obj->reg->dir[pos].rst; - else - reg = &obj->reg->dir[pos].set; - break; - case GPIO_PRO_DOUT: - if (val == GPIO_OUT_ZERO) - reg = &obj->reg->dout[pos].rst; - else - reg = &obj->reg->dout[pos].set; - break; - default: - return -ERINVAL; - } - - mmio_write_16((uintptr_t)reg, data); - - return RSUCCESS; -} - -static int32_t mt_set_gpio_ext(uint32_t pin, uint32_t property, uint32_t val) -{ - uint32_t pos = 0; - uint32_t bit = 0; - struct mt_gpioext_obj *obj = mt_get_gpioext_obj(); - uint16_t *reg; - uint32_t data = 0; - int ret = 0; - - if (!obj) - return -ERACCESS; - - if (pin >= MAX_GPIO_PIN) - return -ERINVAL; - - if (property >= GPIO_PRO_MAX) - return -ERINVAL; - - pin -= GPIO_EXTEND_START; - pos = pin / MAX_GPIO_REG_BITS; - bit = pin % MAX_GPIO_REG_BITS; - - switch (property) { - case GPIO_PRO_DIR: - if (val == GPIO_DIR_IN) - reg = &obj->reg->dir[pos].rst; - else - reg = &obj->reg->dir[pos].set; - break; - case GPIO_PRO_DOUT: - if (val == GPIO_OUT_ZERO) - reg = &obj->reg->dout[pos].rst; - else - reg = &obj->reg->dout[pos].set; - break; - default: - return -ERINVAL; - } - data = (1L << bit); - ret = gpioext_set_bits(data, reg); - - return ret ? -ERWRAPPER : RSUCCESS; -} - -static void mt_gpio_pin_decrypt(uint32_t *cipher) -{ - if ((*cipher & (0x80000000)) == 0) - INFO("Pin %u decrypt warning!\n", *cipher); - *cipher &= ~(0x80000000); -} - -int32_t mt_set_gpio_out(uint32_t pin, uint32_t output) -{ - uint32_t gp = GPIO_PRO_DOUT; - - mt_gpio_pin_decrypt(&pin); - - return (pin >= GPIO_EXTEND_START) ? - mt_set_gpio_ext(pin, gp, output) : - mt_set_gpio_chip(pin, gp, output); -} - -void gpio_set(uint32_t gpio, int32_t value) -{ - mt_set_gpio_out(gpio, value); -} diff --git a/plat/mediatek/mt8173/drivers/gpio/gpio.h b/plat/mediatek/mt8173/drivers/gpio/gpio.h deleted file mode 100644 index ccc99e1d7..000000000 --- a/plat/mediatek/mt8173/drivers/gpio/gpio.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __PLAT_DRIVER_GPIO_H__ -#define __PLAT_DRIVER_GPIO_H__ - -#include - -enum { - GPIOEXT_BASE = 0xC000, -}; - -/* Error Code No. */ -enum { - RSUCCESS = 0, - ERACCESS, - ERINVAL, - ERWRAPPER, -}; - -enum { - GPIO_UNSUPPORTED = -1, - - GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, - GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15, - GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23, - GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31, - GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39, - GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47, - GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55, - GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63, - GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71, - GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79, - GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87, - GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95, - GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103, - GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111, - GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119, - GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127, - GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, - - GPIOEXT0, GPIOEXT1, GPIOEXT2, GPIOEXT3, GPIOEXT4, GPIOEXT5, - GPIOEXT6, GPIOEXT7, GPIOEXT8, GPIOEXT9, GPIOEXT10, GPIOEXT11, - GPIOEXT12, GPIOEXT13, GPIOEXT14, GPIOEXT15, GPIOEXT16, GPIOEXT17, - GPIOEXT18, GPIOEXT19, GPIOEXT20, GPIOEXT21, GPIOEXT22, GPIOEXT23, - GPIOEXT24, GPIOEXT25, GPIOEXT26, GPIOEXT27, GPIOEXT28, GPIOEXT29, - GPIOEXT30, GPIOEXT31, GPIOEXT32, GPIOEXT33, GPIOEXT34, GPIOEXT35, - GPIOEXT36, GPIOEXT37, GPIOEXT38, GPIOEXT39, GPIOEXT40, - - GPIO_MAX -}; - -#define MAX_GPIO_PIN GPIO_MAX - -#define GPIO_EXTEND_START GPIOEXT0 - -/* GPIO DIRECTION */ -enum { - GPIO_DIR_UNSUPPORTED = -1, - GPIO_DIR_IN = 0, - GPIO_DIR_OUT = 1, - GPIO_DIR_MAX, - GPIO_DIR_DEFAULT = GPIO_DIR_IN, -}; - -/* GPIO OUTPUT */ -enum { - GPIO_OUT_UNSUPPORTED = -1, - GPIO_OUT_ZERO = 0, - GPIO_OUT_ONE = 1, - GPIO_OUT_MAX, - GPIO_OUT_DEFAULT = GPIO_OUT_ZERO, - GPIO_DATA_OUT_DEFAULT = GPIO_OUT_ZERO, /* compatible with DCT */ -}; - -struct val_regs { - uint16_t val; - uint16_t _align1; - uint16_t set; - uint16_t _align2; - uint16_t rst; - uint16_t _align3[3]; -}; - -struct gpio_regs { - struct val_regs dir[9]; /* 0x0000 ~ 0x008F: 144 bytes */ - uint8_t rsv00[112]; /* 0x0090 ~ 0x00FF: 112 bytes */ - struct val_regs pullen[9]; /* 0x0100 ~ 0x018F: 144 bytes */ - uint8_t rsv01[112]; /* 0x0190 ~ 0x01FF: 112 bytes */ - struct val_regs pullsel[9]; /* 0x0200 ~ 0x028F: 144 bytes */ - uint8_t rsv02[112]; /* 0x0290 ~ 0x02FF: 112 bytes */ - uint8_t rsv03[256]; /* 0x0300 ~ 0x03FF: 256 bytes */ - struct val_regs dout[9]; /* 0x0400 ~ 0x048F: 144 bytes */ - uint8_t rsv04[112]; /* 0x0490 ~ 0x04FF: 112 bytes */ - struct val_regs din[9]; /* 0x0500 ~ 0x058F: 114 bytes */ - uint8_t rsv05[112]; /* 0x0590 ~ 0x05FF: 112 bytes */ - struct val_regs mode[27]; /* 0x0600 ~ 0x07AF: 432 bytes */ - uint8_t rsv06[336]; /* 0x07B0 ~ 0x08FF: 336 bytes */ - struct val_regs ies[3]; /* 0x0900 ~ 0x092F: 48 bytes */ - struct val_regs smt[3]; /* 0x0930 ~ 0x095F: 48 bytes */ - uint8_t rsv07[160]; /* 0x0960 ~ 0x09FF: 160 bytes */ - struct val_regs tdsel[8]; /* 0x0A00 ~ 0x0A7F: 128 bytes */ - struct val_regs rdsel[6]; /* 0x0A80 ~ 0x0ADF: 96 bytes */ - uint8_t rsv08[32]; /* 0x0AE0 ~ 0x0AFF: 32 bytes */ - struct val_regs drv_mode[10]; /* 0x0B00 ~ 0x0B9F: 160 bytes */ - uint8_t rsv09[96]; /* 0x0BA0 ~ 0x0BFF: 96 bytes */ - struct val_regs msdc0_ctrl0; /* 0x0C00 ~ 0x0C0F: 16 bytes */ - struct val_regs msdc0_ctrl1; /* 0x0C10 ~ 0x0C1F: 16 bytes */ - struct val_regs msdc0_ctrl2; /* 0x0C20 ~ 0x0C2F: 16 bytes */ - struct val_regs msdc0_ctrl5; /* 0x0C30 ~ 0x0C3F: 16 bytes */ - struct val_regs msdc1_ctrl0; /* 0x0C40 ~ 0x0C4F: 16 bytes */ - struct val_regs msdc1_ctrl1; /* 0x0C50 ~ 0x0C5F: 16 bytes */ - struct val_regs msdc1_ctrl2; /* 0x0C60 ~ 0x0C6F: 16 bytes */ - struct val_regs msdc1_ctrl5; /* 0x0C70 ~ 0x0C7F: 16 bytes */ - struct val_regs msdc2_ctrl0; /* 0x0C80 ~ 0x0C8F: 16 bytes */ - struct val_regs msdc2_ctrl1; /* 0x0C90 ~ 0x0C9F: 16 bytes */ - struct val_regs msdc2_ctrl2; /* 0x0CA0 ~ 0x0CAF: 16 bytes */ - struct val_regs msdc2_ctrl5; /* 0x0CB0 ~ 0x0CBF: 16 bytes */ - struct val_regs msdc3_ctrl0; /* 0x0CC0 ~ 0x0CCF: 16 bytes */ - struct val_regs msdc3_ctrl1; /* 0x0CD0 ~ 0x0CDF: 16 bytes */ - struct val_regs msdc3_ctrl2; /* 0x0CE0 ~ 0x0CEF: 16 bytes */ - struct val_regs msdc3_ctrl5; /* 0x0CF0 ~ 0x0CFF: 16 bytes */ - struct val_regs msdc0_ctrl3; /* 0x0D00 ~ 0x0D0F: 16 bytes */ - struct val_regs msdc0_ctrl4; /* 0x0D10 ~ 0x0D1F: 16 bytes */ - struct val_regs msdc1_ctrl3; /* 0x0D20 ~ 0x0D2F: 16 bytes */ - struct val_regs msdc1_ctrl4; /* 0x0D30 ~ 0x0D3F: 16 bytes */ - struct val_regs msdc2_ctrl3; /* 0x0D40 ~ 0x0D4F: 16 bytes */ - struct val_regs msdc2_ctrl4; /* 0x0D50 ~ 0x0D5F: 16 bytes */ - struct val_regs msdc3_ctrl3; /* 0x0D60 ~ 0x0D6F: 16 bytes */ - struct val_regs msdc3_ctrl4; /* 0x0D70 ~ 0x0D7F: 16 bytes */ - uint8_t rsv10[64]; /* 0x0D80 ~ 0x0DBF: 64 bytes */ - struct val_regs exmd_ctrl[1]; /* 0x0DC0 ~ 0x0DCF: 16 bytes */ - uint8_t rsv11[48]; /* 0x0DD0 ~ 0x0DFF: 48 bytes */ - struct val_regs kpad_ctrl[2]; /* 0x0E00 ~ 0x0E1F: 32 bytes */ - struct val_regs hsic_ctrl[4]; /* 0x0E20 ~ 0x0E5F: 64 bytes */ -}; - -struct ext_val_regs { - uint16_t val; - uint16_t set; - uint16_t rst; - uint16_t _align; -}; - -struct gpioext_regs { - struct ext_val_regs dir[4]; /* 0x0000 ~ 0x001F: 32 bytes */ - struct ext_val_regs pullen[4]; /* 0x0020 ~ 0x003F: 32 bytes */ - struct ext_val_regs pullsel[4]; /* 0x0040 ~ 0x005F: 32 bytes */ - struct ext_val_regs dinv[4]; /* 0x0060 ~ 0x007F: 32 bytes */ - struct ext_val_regs dout[4]; /* 0x0080 ~ 0x009F: 32 bytes */ - struct ext_val_regs din[4]; /* 0x00A0 ~ 0x00BF: 32 bytes */ - struct ext_val_regs mode[10]; /* 0x00C0 ~ 0x010F: 80 bytes */ -}; - -/* GPIO Driver interface */ -void gpio_set(uint32_t gpio, int32_t value); - -#endif /* __PLAT_DRIVER_GPIO_H__ */ diff --git a/plat/mediatek/mt8173/plat_pm.c b/plat/mediatek/mt8173/plat_pm.c index be33c9114..6bb8a9b5a 100644 --- a/plat/mediatek/mt8173/plat_pm.c +++ b/plat/mediatek/mt8173/plat_pm.c @@ -48,7 +48,6 @@ #include #include #include -#include "drivers/gpio/gpio.h" struct core_context { unsigned long timer_data[8]; @@ -478,7 +477,6 @@ static void __dead2 plat_system_off(void) { INFO("MTK System Off\n"); - gpio_set(GPIO120, GPIO_OUT_ZERO); rtc_bbpu_power_down(); wfi(); diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk index 7f07c15be..4169823f5 100644 --- a/plat/mediatek/mt8173/platform.mk +++ b/plat/mediatek/mt8173/platform.mk @@ -32,7 +32,6 @@ MTK_PLAT := plat/mediatek MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ - -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/mtcmos/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ -I${MTK_PLAT_SOC}/drivers/rtc/ \ @@ -60,7 +59,6 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/aarch64/platform_common.c \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ - ${MTK_PLAT_SOC}/drivers/gpio/gpio.c \ ${MTK_PLAT_SOC}/drivers/mtcmos/mtcmos.c \ ${MTK_PLAT_SOC}/drivers/pmic/pmic_wrap_init.c \ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ From b99d961c7db6558d36e08d1656662226a8481a85 Mon Sep 17 00:00:00 2001 From: Jimmy Huang Date: Mon, 16 Nov 2015 13:44:31 +0800 Subject: [PATCH 3/3] mt8173: support big core PLL control in system suspend flow This patch adds big core ARMPLL control in system suspend flow. Change-Id: I27a45dbbb360f17ff0b524a125630358ee2277e2 Signed-off-by: Louis Yu Signed-off-by: Jimmy Huang --- plat/mediatek/mt8173/drivers/rtc/rtc.c | 4 +-- .../mediatek/mt8173/drivers/spm/spm_suspend.c | 30 +++++++++++++++++-- plat/mediatek/mt8173/include/mt8173_def.h | 1 + 3 files changed, 31 insertions(+), 4 deletions(-) diff --git a/plat/mediatek/mt8173/drivers/rtc/rtc.c b/plat/mediatek/mt8173/drivers/rtc/rtc.c index e171863da..daaac42c6 100644 --- a/plat/mediatek/mt8173/drivers/rtc/rtc.c +++ b/plat/mediatek/mt8173/drivers/rtc/rtc.c @@ -95,8 +95,8 @@ void rtc_bbpu_power_down(void) if (Writeif_unlock()) { RTC_Write(RTC_BBPU, bbpu); if (!Write_trigger()) - assert(1); + assert(0); } else { - assert(1); + assert(0); } } diff --git a/plat/mediatek/mt8173/drivers/spm/spm_suspend.c b/plat/mediatek/mt8173/drivers/spm/spm_suspend.c index 6bf37f3a5..843b5f9eb 100644 --- a/plat/mediatek/mt8173/drivers/spm/spm_suspend.c +++ b/plat/mediatek/mt8173/drivers/spm/spm_suspend.c @@ -29,6 +29,9 @@ */ #include #include +#include +#include +#include #include #include @@ -38,8 +41,6 @@ * This driver controls the system power in system suspend flow. */ -#define WAIT_UART_ACK_TIMES 80 /* 80 * 10us */ - #define WAKE_SRC_FOR_SUSPEND \ (WAKE_SRC_KP | WAKE_SRC_EINT | WAKE_SRC_MD32 | \ WAKE_SRC_USB_CD | WAKE_SRC_USB_PDN | WAKE_SRC_THERM | \ @@ -50,6 +51,13 @@ #define spm_is_wakesrc_invalid(wakesrc) \ (!!((unsigned int)(wakesrc) & 0xc0003803)) +#define ARMCA15PLL_CON0 (APMIXED_BASE + 0x200) +#define ARMCA15PLL_CON1 (APMIXED_BASE + 0x204) +#define ARMCA15PLL_PWR_CON0 (APMIXED_BASE + 0x20c) +#define ARMCA15PLL_PWR_ON (1U << 0) +#define ARMCA15PLL_ISO_EN (1U << 1) +#define ARMCA15PLL_EN (1U << 0) + const unsigned int spm_flags = SPM_DUALVCORE_PDN_DIS | SPM_PASR_DIS | SPM_DPD_DIS | SPM_CPU_DVS_DIS | SPM_OPT | SPM_INFRA_PDN_DIS; @@ -293,8 +301,23 @@ static enum wake_reason_t go_to_sleep_after_wfi(void) return last_wr; } +static void bigcore_pll_on(void) +{ + mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); + mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); + mmio_setbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); +} + +static void bigcore_pll_off(void) +{ + mmio_clrbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); + mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); + mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); +} + void spm_system_suspend(void) { + bigcore_pll_off(); spm_lock_get(); go_to_sleep_before_wfi(spm_flags); set_suspend_ready(); @@ -308,4 +331,7 @@ void spm_system_suspend_finish(void) INFO("spm_wake_reason=%d\n", spm_wake_reason); clear_all_ready(); spm_lock_release(); + bigcore_pll_on(); + /* Add 20us delay for turning on PLL*/ + udelay(20); } diff --git a/plat/mediatek/mt8173/include/mt8173_def.h b/plat/mediatek/mt8173/include/mt8173_def.h index 71668c75e..39bab1499 100644 --- a/plat/mediatek/mt8173/include/mt8173_def.h +++ b/plat/mediatek/mt8173/include/mt8173_def.h @@ -46,6 +46,7 @@ #define RGU_BASE (IO_PHYS + 0x7000) #define PMIC_WRAP_BASE (IO_PHYS + 0xD000) #define MCUCFG_BASE (IO_PHYS + 0x200000) +#define APMIXED_BASE (IO_PHYS + 0x209000) #define TRNG_BASE (IO_PHYS + 0x20F000) #define MT_GIC_BASE (IO_PHYS + 0x220000) #define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000)