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fix(spm-mm): carve out NS buffer TZC400 region

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SPM-MM defines AP TZC-400 regions as such:

1: 0xff000000  0xffffffff   S
2: 0x80000000  0xfeffffff   NS
3: 0x880000000 0xfffffffff  NS
4: 0xff600000  0xff60ffff   NS

Region 4 (using filter 0) defines the SPM NS shared buffer between
normal world and secure world.
However region 4 overlaps with region 1 (using filter 0) defined as
secure.
It is forbidden to define overlapping regions beyond region 0 for the
same filter. This is reported as a violation in the TZC-400 controller.

With FVP models < 11.25 the error is latent but not reported to the PE
(reason for this behavior is unclear).
With greater FVP model version the error is reported as an asynchronous
external abort (SError exception).

By carving out the SPM NS shared region (with regions as defined below),
the violation is no longer reported and test passed with recent FVP
models:

1: 0x80000000  0xfeffffff   NS
2: 0xff000000  0xff5fffff   S
3: 0xff600000  0xff60ffff   NS
4: 0xff610000  0xffffffff   S
5: 0x880000000 0xfffffffff  NS

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idc3370803ad204ac29efeded77305e52e17cc1c1
This commit is contained in:
Olivier Deprez 2024-06-11 14:50:12 +02:00
parent 1e34c3bca2
commit 1922875233
1 changed files with 7 additions and 5 deletions
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12
include/plat/arm/common/plat_arm.h
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@ -69,14 +69,16 @@ typedef struct arm_gpt_info {
#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
#define ARM_TZC_REGIONS_DEF \
{ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
TZC_REGION_S_RDWR, 0}, \
{ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
PLAT_ARM_TZC_NS_DEV_ACCESS}, \
{ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
PLAT_ARM_TZC_NS_DEV_ACCESS}, \
{ARM_AP_TZC_DRAM1_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE - 1), \
TZC_REGION_S_RDWR, 0}, \
{PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
PLAT_SP_IMAGE_NS_BUF_SIZE - 1), TZC_REGION_S_NONE, \
PLAT_ARM_TZC_NS_DEV_ACCESS}, \
{PLAT_SP_IMAGE_STACK_BASE, ARM_EL3_TZC_DRAM1_END, \
TZC_REGION_S_RDWR, 0}, \
{ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
PLAT_ARM_TZC_NS_DEV_ACCESS}
#elif ENABLE_RME