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drivers: marvell Add support for Armada-37xx UART
Introduce driver for Marvell Armada-37xx UART console Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
This commit is contained in:
Konstantin Porotchkin
parent
6f8de19fba
commit
19112b795e
2 changed files with 223 additions and 0 deletions
168
drivers/marvell/uart/a3700_console.S
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168
drivers/marvell/uart/a3700_console.S
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/*
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* Copyright (C) 2016 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <asm_macros.S>
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#include <a3700_console.h>
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.globl console_core_init
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.globl console_core_putc
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.globl console_core_getc
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.globl console_core_flush
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/* -----------------------------------------------
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* int console_core_init(unsigned long base_addr,
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* unsigned int uart_clk, unsigned int baud_rate)
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* Function to initialize the console without a
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* C Runtime to print debug information. This
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* function will be accessed by console_init and
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* crash reporting.
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* In: x0 - console base address
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* w1 - Uart clock in Hz
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* w2 - Baud rate
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* Out: return 1 on success
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* Clobber list : x1, x2, x3
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* -----------------------------------------------
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*/
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func console_core_init
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/* Check the input base address */
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cbz x0, init_fail
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/* Check baud rate and uart clock for sanity */
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cbz w1, init_fail
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cbz w2, init_fail
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/* Program the baudrate */
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/* Divisor = Uart clock / (16 * baudrate) */
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lsl w2, w2, #4
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udiv w2, w1, w2
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and w2, w2, #0x3ff
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ldr w3, [x0, #UART_BAUD_REG]
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bic w3, w3, 0x3ff
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orr w3, w3, w2
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str w3, [x0, #UART_BAUD_REG]/* set baud rate divisor */
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/* Set UART to default 16X scheme */
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mov w3, #0
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str w3, [x0, #UART_POSSR_REG]
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/*
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* Wait for the TX FIFO to be empty. If wait for 20ms, the TX FIFO is
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* still not empty, TX FIFO will reset by all means.
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*/
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mov w1, #20 /* max time out 20ms */
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2:
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/* Check whether TX FIFO is empty */
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ldr w3, [x0, #UART_STATUS_REG]
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and w3, w3, #UARTLSR_TXFIFOEMPTY
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cmp w3, #0
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b.ne 4f
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/* Delay */
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mov w2, #30000
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3:
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sub w2, w2, #1
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cmp w2, #0
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b.ne 3b
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/* Check whether 10ms is waited */
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sub w1, w1, #1
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cmp w1, #0
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b.ne 2b
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4:
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/* Reset FIFO */
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mov w3, #UART_CTRL_RXFIFO_RESET
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orr w3, w3, #UART_CTRL_TXFIFO_RESET
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str w3, [x0, #UART_CTRL_REG]
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/* Delay */
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mov w2, #2000
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1:
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sub w2, w2, #1
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cmp w2, #0
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b.ne 1b
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/* No Parity, 1 Stop */
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mov w3, #0
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str w3, [x0, #UART_CTRL_REG]
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mov w0, #1
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ret
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init_fail:
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mov w0, #0
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ret
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endfunc console_core_init
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/* --------------------------------------------------------
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* int console_core_putc(int c, unsigned int base_addr)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In : w0 - character to be printed
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* x1 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : x2
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* --------------------------------------------------------
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*/
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func console_core_putc
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/* Check the input parameter */
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cbz x1, putc_error
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/* Prepend '\r' to '\n' */
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cmp w0, #0xA
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b.ne 2f
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/* Check if the transmit FIFO is full */
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1: ldr w2, [x1, #UART_STATUS_REG]
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and w2, w2, #UARTLSR_TXFIFOFULL
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cmp w2, #UARTLSR_TXFIFOFULL
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b.eq 1b
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mov w2, #0xD /* '\r' */
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str w2, [x1, #UART_TX_REG]
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/* Check if the transmit FIFO is full */
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2: ldr w2, [x1, #UART_STATUS_REG]
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and w2, w2, #UARTLSR_TXFIFOFULL
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cmp w2, #UARTLSR_TXFIFOFULL
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b.eq 2b
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str w0, [x1, #UART_TX_REG]
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ret
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putc_error:
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mov w0, #-1
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ret
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endfunc console_core_putc
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/* ---------------------------------------------
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* int console_core_getc(void)
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* Function to get a character from the console.
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* It returns the character grabbed on success
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* or -1 on error.
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* In : w0 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func console_core_getc
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/* Check if the receive FIFO is empty */
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ret
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getc_error:
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mov w0, #-1
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ret
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endfunc console_core_getc
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/* ---------------------------------------------
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* int console_core_flush(uintptr_t base_addr)
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* Function to force a write of all buffered
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* data that hasn't been output.
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* In : x0 - console base address
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* Out : return -1 on error else return 0.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func console_core_flush
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/* Placeholder */
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mov w0, #0
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ret
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endfunc console_core_flush
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55
drivers/marvell/uart/a3700_console.h
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55
drivers/marvell/uart/a3700_console.h
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/*
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* Copyright (C) 2016 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef __A3700_CONSOLE_H__
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#define __A3700_CONSOLE_H__
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/* MVEBU UART Registers */
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#define UART_RX_REG 0x00
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#define UART_TX_REG 0x04
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#define UART_CTRL_REG 0x08
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#define UART_STATUS_REG 0x0c
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#define UART_BAUD_REG 0x10
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#define UART_POSSR_REG 0x14
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/* FIFO Control Register bits */
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#define UARTFCR_FIFOMD_16450 (0 << 6)
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#define UARTFCR_FIFOMD_16550 (1 << 6)
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#define UARTFCR_RXTRIG_1 (0 << 6)
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#define UARTFCR_RXTRIG_4 (1 << 6)
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#define UARTFCR_RXTRIG_8 (2 << 6)
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#define UARTFCR_RXTRIG_16 (3 << 6)
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#define UARTFCR_TXTRIG_1 (0 << 4)
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#define UARTFCR_TXTRIG_4 (1 << 4)
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#define UARTFCR_TXTRIG_8 (2 << 4)
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#define UARTFCR_TXTRIG_16 (3 << 4)
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#define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */
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#define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */
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#define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */
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#define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */
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/* Line Control Register bits */
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#define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */
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#define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */
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#define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */
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#define UARTLCR_EVEN (1 << 4) /* Even Parity Format */
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#define UARTLCR_PAR (1 << 3) /* Parity */
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#define UARTLCR_STOP (1 << 2) /* Stop Bit */
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#define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */
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#define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */
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#define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */
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#define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */
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/* Line Status Register bits */
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#define UARTLSR_TXFIFOFULL (1 << 11) /* Tx Fifo Full */
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/* UART Control Register bits */
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#define UART_CTRL_RXFIFO_RESET (1 << 14)
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#define UART_CTRL_TXFIFO_RESET (1 << 15)
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#define UARTLSR_TXFIFOEMPTY (1 << 6)
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#endif /* __A3700_CONSOLE_H__ */
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