From 8118078b71583e01a486da01f1bf369b4fde3c59 Mon Sep 17 00:00:00 2001
From: Ahmed Azeem <ahmed.azeem@arm.com>
Date: Tue, 15 Oct 2024 10:31:12 +0100
Subject: [PATCH] feat(cpus): add support for cortex-a720ae

Add the basic CPU library code to support Cortex-A720AE.
The overall library code is adapted based on Cortex-A720 code.

Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Change-Id: I3d64dc5a3098cc823e656a5ad3ea05cd71598dc6
---
 include/lib/cpus/aarch64/cortex_a720_ae.h | 23 ++++++++
 lib/cpus/aarch64/cortex_a720_ae.S         | 65 +++++++++++++++++++++++
 plat/arm/board/fvp/platform.mk            |  1 +
 3 files changed, 89 insertions(+)
 create mode 100644 include/lib/cpus/aarch64/cortex_a720_ae.h
 create mode 100644 lib/cpus/aarch64/cortex_a720_ae.S

diff --git a/include/lib/cpus/aarch64/cortex_a720_ae.h b/include/lib/cpus/aarch64/cortex_a720_ae.h
new file mode 100644
index 000000000..c88b1f9c0
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a720_ae.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A720_AE_H
+#define CORTEX_A720_AE_H
+
+#define CORTEX_A720_AE_MIDR				U(0x410FD890)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A720_AE_CPUECTLR_EL1			S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A720_AE_CPUPWRCTLR_EL1			S3_0_C15_C2_7
+#define CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
+
+#endif /* CORTEX_A720_AE_H */
diff --git a/lib/cpus/aarch64/cortex_a720_ae.S b/lib/cpus/aarch64/cortex_a720_ae.S
new file mode 100644
index 000000000..42d49c336
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a720_ae.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a720_ae.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex-A720AE must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_func_start cortex_a720_ae
+	/* Disable speculative loads */
+	msr	SSBS, xzr
+cpu_reset_func_end cortex_a720_ae
+
+	/* ----------------------------------------------------
+	 * HW will do the cache maintenance while powering down
+	 * ----------------------------------------------------
+	 */
+func cortex_a720_ae_core_pwr_dwn
+	/* ---------------------------------------------------
+	 * Enable CPU power down bit in power control register
+	 * ---------------------------------------------------
+	 */
+	sysreg_bit_set CORTEX_A720_AE_CPUPWRCTLR_EL1, CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
+	isb
+	ret
+endfunc cortex_a720_ae_core_pwr_dwn
+
+	/* ---------------------------------------------
+	 * This function provides Cortex-A720AE specific
+	 * register information for crash reporting.
+	 * It needs to return with x6 pointing to
+	 * a list of register names in ascii and
+	 * x8 - x15 having values of registers to be
+	 * reported.
+	 * ---------------------------------------------
+	 */
+.section .rodata.cortex_a720_ae_regs, "aS"
+cortex_a720_ae_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_a720_ae_cpu_reg_dump
+	adr	x6, cortex_a720_ae_regs
+	mrs	x8, CORTEX_A720_AE_CPUECTLR_EL1
+	ret
+endfunc cortex_a720_ae_cpu_reg_dump
+
+declare_cpu_ops cortex_a720_ae, CORTEX_A720_AE_MIDR, \
+	cortex_a720_ae_reset_func, \
+	cortex_a720_ae_core_pwr_dwn
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index feae8029f..439d4f761 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -194,6 +194,7 @@ else
 					lib/cpus/aarch64/cortex_a710.S		\
 					lib/cpus/aarch64/cortex_a715.S		\
 					lib/cpus/aarch64/cortex_a720.S		\
+					lib/cpus/aarch64/cortex_a720_ae.S	\
 					lib/cpus/aarch64/neoverse_n_common.S	\
 					lib/cpus/aarch64/neoverse_n1.S		\
 					lib/cpus/aarch64/neoverse_n2.S		\