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zynqmp: pm: Implement IOCTL APIs for device control
Implement ioctl APIs which uses MMIO operations to configure devices. Below IOCTLs are supported in this patch: * Set tap delay bypass * Set SGMII mode * SD reset * Set SD/MMC tap delay Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
This commit is contained in:
Rajan Vaja
Jolly Shah
parent
f76918a806
commit
1818c02925
3 changed files with 272 additions and 0 deletions
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@ -140,6 +140,195 @@ static enum pm_ret_status pm_ioctl_config_tcm_comb(unsigned int value)
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return PM_RET_SUCCESS;
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}
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/**
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* pm_ioctl_set_tapdelay_bypass() - Enable/Disable tap delay bypass
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* @type Type of tap delay to enable/disable (e.g. QSPI)
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* @value Enable/Disable
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*
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* This function enable/disable tap delay bypass.
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*
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* @return Returns status, either success or error+reason
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*/
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static enum pm_ret_status pm_ioctl_set_tapdelay_bypass(unsigned int type,
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unsigned int value)
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{
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if ((value != PM_TAPDELAY_BYPASS_ENABLE &&
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value != PM_TAPDELAY_BYPASS_DISABLE) || type >= PM_TAPDELAY_MAX)
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return PM_RET_ERROR_ARGS;
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return pm_mmio_write(IOU_TAPDLY_BYPASS, TAP_DELAY_MASK, value << type);
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}
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/**
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* pm_ioctl_set_sgmii_mode() - Set SGMII mode for the GEM device
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* @nid Node ID of the device
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* @value Enable/Disable
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*
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* This function enable/disable SGMII mode for the GEM device.
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* While enabling SGMII mode, it also ties the GEM PCS Signal
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* Detect to 1 and selects EMIO for RX clock generation.
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*
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* @return Returns status, either success or error+reason
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*/
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static enum pm_ret_status pm_ioctl_set_sgmii_mode(enum pm_node_id nid,
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unsigned int value)
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{
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unsigned int val, mask, shift;
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int ret;
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if (value != PM_SGMII_DISABLE && value != PM_SGMII_ENABLE)
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return PM_RET_ERROR_ARGS;
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switch (nid) {
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case NODE_ETH_0:
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shift = 0;
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break;
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case NODE_ETH_1:
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shift = 1;
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break;
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case NODE_ETH_2:
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shift = 2;
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break;
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case NODE_ETH_3:
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shift = 3;
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break;
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default:
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return PM_RET_ERROR_ARGS;
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}
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if (value == PM_SGMII_DISABLE) {
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mask = GEM_SGMII_MASK << GEM_CLK_CTRL_OFFSET * shift;
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ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, 0);
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} else {
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/* Tie the GEM PCS Signal Detect to 1 */
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mask = SGMII_SD_MASK << SGMII_SD_OFFSET * shift;
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val = SGMII_PCS_SD_1 << SGMII_SD_OFFSET * shift;
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ret = pm_mmio_write(IOU_GEM_CTRL, mask, val);
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if (ret)
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return ret;
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/* Set the GEM to SGMII mode */
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mask = GEM_CLK_CTRL_MASK << GEM_CLK_CTRL_OFFSET * shift;
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val = GEM_RX_SRC_SEL_GTR | GEM_SGMII_MODE;
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val <<= GEM_CLK_CTRL_OFFSET * shift;
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ret = pm_mmio_write(IOU_GEM_CLK_CTRL, mask, val);
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}
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return ret;
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}
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/**
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* pm_ioctl_sd_dll_reset() - Reset DLL logic
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* @nid Node ID of the device
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* @type Reset type
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*
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* This function resets DLL logic for the SD device.
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*
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* @return Returns status, either success or error+reason
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*/
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static enum pm_ret_status pm_ioctl_sd_dll_reset(enum pm_node_id nid,
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unsigned int type)
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{
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unsigned int mask, val;
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int ret;
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if (nid == NODE_SD_0) {
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mask = ZYNQMP_SD0_DLL_RST_MASK;
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val = ZYNQMP_SD0_DLL_RST;
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} else if (nid == NODE_SD_1) {
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mask = ZYNQMP_SD1_DLL_RST_MASK;
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val = ZYNQMP_SD1_DLL_RST;
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} else {
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return PM_RET_ERROR_ARGS;
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}
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switch (type) {
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case PM_DLL_RESET_ASSERT:
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case PM_DLL_RESET_PULSE:
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ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, val);
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if (ret)
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return ret;
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if (type == PM_DLL_RESET_ASSERT)
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break;
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mdelay(1);
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case PM_DLL_RESET_RELEASE:
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ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, 0);
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break;
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default:
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ret = PM_RET_ERROR_ARGS;
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}
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return ret;
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}
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/**
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* pm_ioctl_sd_set_tapdelay() - Set tap delay for the SD device
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* @nid Node ID of the device
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* @type Type of tap delay to set (input/output)
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* @value Value to set fot the tap delay
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*
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* This function sets input/output tap delay for the SD device.
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*
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* @return Returns status, either success or error+reason
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*/
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static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
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enum tap_delay_type type,
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unsigned int value)
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{
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unsigned int shift;
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int ret;
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if (nid == NODE_SD_0)
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shift = 0;
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else if (nid == NODE_SD_1)
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shift = ZYNQMP_SD_TAP_OFFSET;
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else
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return PM_RET_ERROR_ARGS;
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ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
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if (ret)
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return ret;
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if (type == PM_TAPDELAY_INPUT) {
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ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
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ZYNQMP_SD_ITAPCHGWIN_MASK << shift,
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ZYNQMP_SD_ITAPCHGWIN << shift);
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if (ret)
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goto reset_release;
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ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
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ZYNQMP_SD_ITAPDLYENA_MASK << shift,
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ZYNQMP_SD_ITAPDLYENA << shift);
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if (ret)
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goto reset_release;
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ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
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ZYNQMP_SD_ITAPDLYSEL_MASK << shift,
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value << shift);
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if (ret)
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goto reset_release;
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ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
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ZYNQMP_SD_ITAPCHGWIN_MASK << shift, 0);
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} else if (type == PM_TAPDELAY_OUTPUT) {
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ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
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ZYNQMP_SD_OTAPDLYENA_MASK << shift,
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ZYNQMP_SD_OTAPDLYENA << shift);
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if (ret)
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goto reset_release;
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ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
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ZYNQMP_SD_OTAPDLYSEL_MASK << shift,
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value << shift);
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} else {
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ret = PM_RET_ERROR_ARGS;
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}
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reset_release:
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ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_RELEASE);
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if (ret)
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return ret;
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return ret;
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}
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/**
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* pm_api_ioctl() - PM IOCTL API for device control and configs
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* @node_id Node ID of the device
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@ -173,6 +362,18 @@ enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
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case IOCTL_TCM_COMB_CONFIG:
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ret = pm_ioctl_config_tcm_comb(arg1);
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break;
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case IOCTL_SET_TAPDELAY_BYPASS:
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ret = pm_ioctl_set_tapdelay_bypass(arg1, arg2);
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break;
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case IOCTL_SET_SGMII_MODE:
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ret = pm_ioctl_set_sgmii_mode(nid, arg1);
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break;
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case IOCTL_SD_DLL_RESET:
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ret = pm_ioctl_sd_dll_reset(nid, arg1);
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break;
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case IOCTL_SET_SD_TAPDELAY:
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ret = pm_ioctl_sd_set_tapdelay(nid, arg1, arg2);
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break;
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default:
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ret = PM_RET_ERROR_NOTSUPPORTED;
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}
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@ -18,6 +18,10 @@ enum pm_ioctl_id {
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IOCTL_SET_RPU_OPER_MODE,
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IOCTL_RPU_BOOT_ADDR_CONFIG,
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IOCTL_TCM_COMB_CONFIG,
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IOCTL_SET_TAPDELAY_BYPASS,
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IOCTL_SET_SGMII_MODE,
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IOCTL_SD_DLL_RESET,
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IOCTL_SET_SD_TAPDELAY,
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};
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enum rpu_oper_mode {
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@ -35,6 +39,34 @@ enum rpu_tcm_comb {
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PM_RPU_TCM_COMB,
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};
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enum tap_delay_signal_type {
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PM_TAPDELAY_NAND_DQS_IN,
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PM_TAPDELAY_NAND_DQS_OUT,
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PM_TAPDELAY_QSPI,
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PM_TAPDELAY_MAX,
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};
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enum tap_delay_bypass_ctrl {
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PM_TAPDELAY_BYPASS_DISABLE,
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PM_TAPDELAY_BYPASS_ENABLE,
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};
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enum sgmii_mode {
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PM_SGMII_DISABLE,
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PM_SGMII_ENABLE,
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};
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enum tap_delay_type {
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PM_TAPDELAY_INPUT,
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PM_TAPDELAY_OUTPUT,
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};
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enum dll_reset_type {
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PM_DLL_RESET_ASSERT,
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PM_DLL_RESET_RELEASE,
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PM_DLL_RESET_PULSE,
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};
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enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
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unsigned int ioctl_id,
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unsigned int arg1,
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@ -186,4 +186,43 @@
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#define ZYNQMP_SLCLAMP_MASK 0x10
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#define ZYNQMP_VINITHI_MASK 0x04
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/* Tap delay bypass */
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#define IOU_TAPDLY_BYPASS 0XFF180390
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#define TAP_DELAY_MASK 0x7
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/* SGMII mode */
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#define IOU_GEM_CTRL 0xFF180360
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#define IOU_GEM_CLK_CTRL 0xFF180308
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#define SGMII_SD_MASK 0x3
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#define SGMII_SD_OFFSET 2
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#define SGMII_PCS_SD_0 0x0
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#define SGMII_PCS_SD_1 0x1
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#define SGMII_PCS_SD_PHY 0x2
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#define GEM_SGMII_MASK 0x4
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#define GEM_CLK_CTRL_MASK 0xF
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#define GEM_CLK_CTRL_OFFSET 5
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#define GEM_RX_SRC_SEL_GTR 0x1
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#define GEM_SGMII_MODE 0x4
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/* SD DLL reset */
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#define ZYNQMP_SD_DLL_CTRL 0xFF180358
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#define ZYNQMP_SD0_DLL_RST_MASK 0x00000004
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#define ZYNQMP_SD0_DLL_RST 0x00000004
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#define ZYNQMP_SD1_DLL_RST_MASK 0x00040000
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#define ZYNQMP_SD1_DLL_RST 0x00040000
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/* SD tap delay */
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#define ZYNQMP_SD_DLL_CTRL 0xFF180358
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#define ZYNQMP_SD_ITAP_DLY 0xFF180314
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#define ZYNQMP_SD_OTAP_DLY 0xFF180318
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#define ZYNQMP_SD_TAP_OFFSET 16
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#define ZYNQMP_SD_ITAPCHGWIN_MASK 0x200
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#define ZYNQMP_SD_ITAPCHGWIN 0x200
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#define ZYNQMP_SD_ITAPDLYENA_MASK 0x100
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#define ZYNQMP_SD_ITAPDLYENA 0x100
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#define ZYNQMP_SD_ITAPDLYSEL_MASK 0xFF
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#define ZYNQMP_SD_OTAPDLYSEL_MASK 0x3F
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#define ZYNQMP_SD_OTAPDLYENA_MASK 0x40
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#define ZYNQMP_SD_OTAPDLYENA 0x40
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#endif /* __ZYNQMP_DEF_H__ */
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