From 81ad3b14b95e019eaa8d89d444680c14ede4d8ab Mon Sep 17 00:00:00 2001 From: Prasad Kummari Date: Fri, 14 Jul 2023 16:32:19 +0530 Subject: [PATCH 1/2] fix(zynqmp): resolve runtime error in TSP TSP(bl32) requires secure interrupts to be handled at S-EL1. Enable the ZynqMP to handle secure interrupts in S-EL1 by setting GICV2_G0_FOR_EL3 to 0 in case of SPD=tspd build option. For ZYNQMP_WDT_RESTART build option GICV2_G0_FOR_EL3 needs to be enabled and thus for ZynqMP GICV2_G0_FOR_EL3 is set to 1 by default. On GICv2, when GICV2_G0_FOR_EL3 is set to 1, Group 0 interrupts target EL3. This allows GICv2 platforms to enable features requiring EL3 interrupt type. This also means that all GICv2 Group 0 interrupts are delivered to EL3, and the Secure Payload interrupts needs to be synchronously handed over to Secure EL1 for handling. Change-Id: I7eb72c6588ab41730a74ece261050840646de037 Signed-off-by: Prasad Kummari --- plat/xilinx/zynqmp/platform.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index 36fa0f844..9c79855f1 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -20,7 +20,7 @@ override WARMBOOT_ENABLE_DCACHE_EARLY := 1 EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT) # pncd SPD requires secure SGI to be handled at EL1 -ifeq (${SPD},pncd) +ifeq (${SPD}, $(filter ${SPD},pncd tspd)) ifeq (${ZYNQMP_WDT_RESTART},1) $(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible") endif From ba5540021a3d69283ee2ee079cf6f4564623c806 Mon Sep 17 00:00:00 2001 From: Prasad Kummari Date: Fri, 14 Jul 2023 16:39:02 +0530 Subject: [PATCH 2/2] chore(zynqmp): remove unused configuration from TSP In ZynqMP, the function zynqmp_config_setup() is common between bl31 and bl32(TSP). This function initializes IPI configuration and prints the chip idcode and revision on the console, which is already done in bl31 and redundant in bl32(TSP). Remove the legacy code, reading the chip idcode and revision information through direct register read. Change-Id: I5da8e75a597ac9c4e1b56346e065d29e2be8787f Signed-off-by: Prasad Kummari --- plat/xilinx/zynqmp/aarch64/zynqmp_common.c | 11 ----------- plat/xilinx/zynqmp/tsp/tsp_plat_setup.c | 3 --- 2 files changed, 14 deletions(-) diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c index a96c378e7..b584031b7 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -229,20 +229,9 @@ static char *zynqmp_get_silicon_idcode_name(void) size_t i, j, len; const char *name = "EG/EV"; -#ifdef IMAGE_BL32 - /* - * For BL32, get the chip id info directly by reading corresponding - * registers instead of making pm call. This has limitation - * that these registers should be configured to have access - * from APU which is default case. - */ - chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); - chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET); -#else if (pm_get_chipid(chipid) != PM_RET_SUCCESS) { return "XCZUUNKN"; } -#endif id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | ZYNQMP_CSU_IDCODE_SVD_MASK); diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c index ed3300b8c..02d0b23f1 100644 --- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c +++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c @@ -28,9 +28,6 @@ void tsp_early_platform_setup(void) &tsp_boot_console); console_set_scope(&tsp_boot_console, CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); - - /* Initialize the platform config for future decision making */ - zynqmp_config_setup(); } /*******************************************************************************