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chore: rename Chaberton to Cortex-A725

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Rename Chaberton to Cortex-A725.

Change-Id: I981b22d3b37f1aa6e25ff1f35aa156fff9c30076
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
This commit is contained in:
Govindraj Raja 2024-05-17 13:35:19 -05:00
parent b690d244f2
commit 16aacab801
4 changed files with 30 additions and 30 deletions
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16
include/lib/cpus/aarch64/cortex_chaberton.h → include/lib/cpus/aarch64/cortex_a725.h
View file

@ -1,23 +1,23 @@
/* /*
* Copyright (c) 2023, Arm Limited. All rights reserved. * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef CORTEX_CHABERTON_H #ifndef CORTEX_A725_H
#define CORTEX_CHABERTON_H #define CORTEX_A725_H
#define CORTEX_CHABERTON_MIDR U(0x410FD870) #define CORTEX_A725_MIDR U(0x410FD870)
/******************************************************************************* /*******************************************************************************
* CPU Extended Control register specific definitions * CPU Extended Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_CHABERTON_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A725_CPUECTLR_EL1 S3_0_C15_C1_4
/******************************************************************************* /*******************************************************************************
* CPU Power Control register specific definitions * CPU Power Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_CHABERTON_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A725_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) #define CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_CHABERTON_H */ #endif /* CORTEX_A725_H */

40
lib/cpus/aarch64/cortex_chaberton.S → lib/cpus/aarch64/cortex_a725.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2023, Arm Limited. All rights reserved. * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,43 +7,43 @@
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <cortex_chaberton.h> #include <cortex_a725.h>
#include <cpu_macros.S> #include <cpu_macros.S>
#include <plat_macros.S> #include <plat_macros.S>
/* Hardware handled coherency */ /* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0 #if HW_ASSISTED_COHERENCY == 0
#error "Cortex Chaberton must be compiled with HW_ASSISTED_COHERENCY enabled" #error "Cortex-A725 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif #endif
/* 64-bit only core */ /* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1 #if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex Chaberton supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif #endif
cpu_reset_func_start cortex_chaberton cpu_reset_func_start cortex_a725
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr
cpu_reset_func_end cortex_chaberton cpu_reset_func_end cortex_a725
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
* ---------------------------------------------------- * ----------------------------------------------------
*/ */
func cortex_chaberton_core_pwr_dwn func cortex_a725_core_pwr_dwn
/* --------------------------------------------------- /* ---------------------------------------------------
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
sysreg_bit_set CORTEX_CHABERTON_CPUPWRCTLR_EL1, CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT sysreg_bit_set CORTEX_A725_CPUPWRCTLR_EL1, CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb isb
ret ret
endfunc cortex_chaberton_core_pwr_dwn endfunc cortex_a725_core_pwr_dwn
errata_report_shim cortex_chaberton errata_report_shim cortex_a725
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex Chaberton specific * This function provides Cortex-A725 specific
* register information for crash reporting. * register information for crash reporting.
* It needs to return with x6 pointing to * It needs to return with x6 pointing to
* a list of register names in ascii and * a list of register names in ascii and
@ -51,16 +51,16 @@ errata_report_shim cortex_chaberton
* reported. * reported.
* --------------------------------------------- * ---------------------------------------------
*/ */
.section .rodata.cortex_chaberton_regs, "aS" .section .rodata.cortex_a725_regs, "aS"
cortex_chaberton_regs: /* The ascii list of register names to be reported */ cortex_a725_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", "" .asciz "cpuectlr_el1", ""
func cortex_chaberton_cpu_reg_dump func cortex_a725_cpu_reg_dump
adr x6, cortex_chaberton_regs adr x6, cortex_a725_regs
mrs x8, CORTEX_CHABERTON_CPUECTLR_EL1 mrs x8, CORTEX_A725_CPUECTLR_EL1
ret ret
endfunc cortex_chaberton_cpu_reg_dump endfunc cortex_a725_cpu_reg_dump
declare_cpu_ops cortex_chaberton, CORTEX_CHABERTON_MIDR, \ declare_cpu_ops cortex_a725, CORTEX_A725_MIDR, \
cortex_chaberton_reset_func, \ cortex_a725_reset_func, \
cortex_chaberton_core_pwr_dwn cortex_a725_core_pwr_dwn

2
plat/arm/board/arm_fpga/platform.mk
View file

@ -77,7 +77,7 @@ else
lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_n2.S \ lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_v1.S \ lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_chaberton.S \ lib/cpus/aarch64/cortex_a725.S \
lib/cpus/aarch64/cortex_blackhawk.S lib/cpus/aarch64/cortex_blackhawk.S
# AArch64/AArch32 cores # AArch64/AArch32 cores

2
plat/arm/board/tc/platform.mk
View file

@ -100,7 +100,7 @@ endif
# CPU libraries for TARGET_PLATFORM=3 # CPU libraries for TARGET_PLATFORM=3
ifeq (${TARGET_PLATFORM}, 3) ifeq (${TARGET_PLATFORM}, 3)
TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \ TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \
lib/cpus/aarch64/cortex_chaberton.S \ lib/cpus/aarch64/cortex_a725.S \
lib/cpus/aarch64/cortex_blackhawk.S lib/cpus/aarch64/cortex_blackhawk.S
endif endif