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Merge changes I00d2de7b,I5ec82646 into integration

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* changes:
  feat(tc): fpga: Enable support for loading FIP image to DRAM
  feat(tc): allow Android load and Boot From RAM
This commit is contained in:
Olivier Deprez 2024-12-05 16:00:37 +01:00 • committed by TrustedFirmware Code Review
commit 15e5c6c91d
3 changed files with 56 additions and 3 deletions
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13
fdts/tc-fpga.dtsi
View file

@ -25,6 +25,19 @@
stdout-path = "serial0:38400n8";
};
#if TC_FPGA_ANDROID_IMG_IN_RAM
reserved-memory {
phram@0x880000000 {
/*
* starting from 0x8_8000_0000 reserve some memory
* android image will be side loaded to this location
*/
reg = <0x8 0x80000000 HI(ANDROID_FS_SIZE) LO(ANDROID_FS_SIZE)>
no-map;
};
};
#endif /* TC_FPGA_ANDROID_IMG_IN_RAM */
ethernet: ethernet@ETHERNET_ADDR {
compatible = "smsc,lan9115";
phy-mode = "mii";

34
plat/arm/board/tc/include/platform_def.h
View file

@ -207,7 +207,21 @@
#if defined(TARGET_FLAVOUR_FPGA)
#undef V2M_FLASH0_BASE
#undef V2M_FLASH0_SIZE
#if TC_FPGA_FIP_IMG_IN_RAM
/*
* Note that this is just used for the FIP, which is not required
* anymore once Linux has commenced booting. So we are safe allowing
* Linux to also make use of this memory and it doesn't need to be
* carved out of the devicetree.
*
* This only needs to match the RAM load address that we give the FIP
* on either the FPGA or FVP command line so there is no need to link
* it to say halfway through the RAM or anything like that.
*/
#define V2M_FLASH0_BASE UL(0xB0000000)
#else
#define V2M_FLASH0_BASE UL(0x0C000000)
#endif
#define V2M_FLASH0_SIZE UL(0x02000000)
#endif
@ -242,10 +256,28 @@
#if TARGET_PLATFORM <= 2
#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#elif TARGET_PLATFORM >= 3
#if TC_FPGA_ANDROID_IMG_IN_RAM
/* 10GB reserved for system+userdata+vendor images */
#define SYSTEM_IMAGE_SIZE 0xC0000000 /* 3GB */
#define USERDATA_IMAGE_SIZE 0x140000000 /* 5GB */
#define VENDOR_IMAGE_SIZE 0x20000000 /* 512MB */
#define RESERVE_IMAGE_SIZE 0x60000000 /* 1.5GB */
#define ANDROID_FS_SIZE (SYSTEM_IMAGE_SIZE + \
USERDATA_IMAGE_SIZE + \
VENDOR_IMAGE_SIZE + RESERVE_IMAGE_SIZE)
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) + ANDROID_FS_SIZE
#define PLAT_ARM_DRAM2_SIZE ULL(0x380000000) - ANDROID_FS_SIZE
#else
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#endif /* TARGET_PLATFORM >= 3 */
#define PLAT_ARM_DRAM2_SIZE ULL(0x380000000)
#endif /* TC_FPGA_ANDROID_IMG_IN_RAM */
#endif /* TARGET_VERSION >= 3 */
#define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL)
#define TC_NS_MTE_SIZE (256 * SZ_1M)

8
plat/arm/board/tc/platform.mk
View file

@ -77,12 +77,20 @@ ifeq ($(filter ${TARGET_FLAVOUR}, fvp fpga),)
$(error TARGET_FLAVOUR must be fvp or fpga)
endif
# Support for loading Android Image to DRAM
TC_FPGA_ANDROID_IMG_IN_RAM := 0
# Support Loading of FIP image to DRAM
TC_FPGA_FIP_IMG_IN_RAM := 0
$(eval $(call add_defines, \
TARGET_PLATFORM \
TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \
TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \
TC_DPU_USE_SCMI_CLK \
TC_SCMI_PD_CTRL_EN \
TC_FPGA_ANDROID_IMG_IN_RAM \
TC_FPGA_FIP_IMG_IN_RAM \
))
CSS_LOAD_SCP_IMAGES := 1