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feat(plat/arm/css): add per-cpu power down support for warm reset

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Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.

Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
This commit is contained in:
Pranav Madhu 2022-07-27 12:49:24 +05:30
parent 5cf9cc130a
commit 158ed580bd
4 changed files with 39 additions and 3 deletions
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5
docs/plat/arm/arm-build-options.rst
View file

@ -152,6 +152,11 @@ Arm CSS Platform-Specific Build Options
to select the appropriate platform variant for the build. The range of
valid values is platform specific.
- ``CSS_SYSTEM_GRACEFUL_RESET``: Build option to enable graceful powerdown of
CPU core on reset. This build option can be used on CSS platforms that
require all the CPUs to execute the CPU specific power down sequence to
complete a warm reboot sequence in which only the CPUs are power cycled.
--------------
.. |FIP in a GPT image| image:: ../../resources/diagrams/FIP_in_a_GPT_image.png

6
include/plat/arm/css/common/css_pm.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,6 +12,9 @@
#include <lib/psci/psci.h>
/* SGI used to trigger per-core power down request */
#define CSS_CPU_PWR_DOWN_REQ_INTR ARM_IRQ_SEC_SGI_7
/* Macros to read the CSS power domain state */
#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
@ -37,6 +40,7 @@ void __dead2 css_system_reset(void);
void css_cpu_standby(plat_local_state_t cpu_state);
void css_get_sys_suspend_power_state(psci_power_state_t *req_state);
int css_node_hw_state(u_register_t mpidr, unsigned int power_level);
void css_setup_cpu_pwr_down_intr(void);
/*
* This mapping array has to be exported by the platform. Each element at

8
plat/arm/css/common/css_common.mk
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -88,3 +88,9 @@ CSS_NON_SECURE_UART := 0
$(eval $(call assert_boolean,CSS_NON_SECURE_UART))
$(eval $(call add_define,CSS_NON_SECURE_UART))
# Process CSS_SYSTEM_GRACEFUL_RESET flag
# This build option can be used on CSS platforms that require all the CPUs
# to execute the CPU specific power down sequence to complete a warm reboot
# sequence in which only the CPUs are power cycled.
CSS_SYSTEM_GRACEFUL_RESET := 0
$(eval $(call add_define,CSS_SYSTEM_GRACEFUL_RESET))

23
plat/arm/css/common/css_pm.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,12 +9,15 @@
#include <platform_def.h>
#include <arch_helpers.h>
#include <bl31/interrupt_mgmt.h>
#include <common/debug.h>
#include <drivers/arm/css/css_scp.h>
#include <lib/cassert.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/arm/css/common/css_pm.h>
#include <plat/common/platform.h>
/* Allow CSS platforms to override `plat_arm_psci_pm_ops` */
#pragma weak plat_arm_psci_pm_ops
@ -110,6 +113,9 @@ void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
/* Enable the gic cpu interface */
plat_arm_gic_cpuif_enable();
/* Setup the CPU power down request interrupt for secondary core(s) */
css_setup_cpu_pwr_down_intr();
}
/*******************************************************************************
@ -331,6 +337,21 @@ static int css_translate_power_state_by_mpidr(u_register_t mpidr,
return arm_validate_power_state(power_state, output_state);
}
/*
* Setup the SGI interrupt that will be used trigger the execution of power
* down sequence for all the secondary cores. This interrupt is setup to be
* handled in EL3 context at a priority defined by the platform.
*/
void css_setup_cpu_pwr_down_intr(void)
{
#if CSS_SYSTEM_GRACEFUL_RESET
plat_ic_set_interrupt_type(CSS_CPU_PWR_DOWN_REQ_INTR, INTR_TYPE_EL3);
plat_ic_set_interrupt_priority(CSS_CPU_PWR_DOWN_REQ_INTR,
PLAT_REBOOT_PRI);
plat_ic_enable_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR);
#endif
}
/*******************************************************************************
* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
* platform will take care of registering the handlers with PSCI.