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fix(plat/marvell/a3720/uart): configure UART after TX FIFO reset

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If TX FIFO is not empty, do not touch UART settings and let UART HW
transmit remaining bytes from TX FIFO. New UART settings are then set
only after TX FIFO is reset.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2976c0a4fbb841d3a79d42ef67c06e70174afc3b
This commit is contained in:
Pali Rohár 2021-11-15 10:53:21 +01:00 • committed by Manish Pandey
parent 7c85a75729
commit 15546dbf40
1 changed files with 13 additions and 13 deletions
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26
drivers/marvell/uart/a3700_console.S
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@ -44,19 +44,6 @@ func console_a3700_core_init
cbz w1, init_fail cbz w1, init_fail
cbz w2, init_fail cbz w2, init_fail
/* Program the baudrate */
/* Divisor = Round(Uartclock / (16 * baudrate)) */
lsl w2, w2, #4
add w1, w1, w2, lsr #1
udiv w2, w1, w2
and w2, w2, #0x3ff /* clear all other bits to use default clock */
str w2, [x0, #UART_BAUD_REG]/* set baud rate divisor */
/* Set UART to default 16X scheme */
mov w3, #0
str w3, [x0, #UART_POSSR_REG]
/* /*
* Wait for the TX (THR and TSR) to be empty. If wait for 3ms, the TX FIFO is * Wait for the TX (THR and TSR) to be empty. If wait for 3ms, the TX FIFO is
* still not empty, TX FIFO will reset by all means. * still not empty, TX FIFO will reset by all means.
@ -94,6 +81,19 @@ func console_a3700_core_init
cmp w3, #0 cmp w3, #0
b.ne 1b b.ne 1b
/* Program the baudrate */
/* Divisor = Round(Uartclock / (16 * baudrate)) */
lsl w2, w2, #4
add w1, w1, w2, lsr #1
udiv w2, w1, w2
and w2, w2, #0x3ff /* clear all other bits to use default clock */
str w2, [x0, #UART_BAUD_REG]/* set baud rate divisor */
/* Set UART to default 16X scheme */
mov w3, #0
str w3, [x0, #UART_POSSR_REG]
/* No Parity, 1 Stop */ /* No Parity, 1 Stop */
mov w3, #0 mov w3, #0
str w3, [x0, #UART_CTRL_REG] str w3, [x0, #UART_CTRL_REG]