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feat(plat/rcar3): add process of SSCG setting for R-Car D3

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- Added the condition where output the SSCG (MD12) setting
  to log for R-Car D3.
- Added the process to switching the bit rate of SCIF by the
  SSCG (MD12) setting value for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9
This commit is contained in:
Toshiyuki Ogasahara 2021-07-12 19:19:39 +09:00 • committed by Marek Vasut
parent 7d58aed3b0
commit 14f0a08172
2 changed files with 20 additions and 8 deletions
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26
drivers/renesas/common/scif/scif.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -79,7 +79,7 @@
SCSMR_STOP_1 + \
SCSMR_CKS_DIV1)
#define SCBRR_115200BPS (17)
#define SCBRR_115200BPSON (16)
#define SCBRR_115200BPS_D3_SSCG (16)
#define SCBRR_115200BPS_E3_SSCG (15)
#define SCBRR_230400BPS (8)
@ -216,26 +216,38 @@ func console_rcar_init
and w1, w1, #PRR_PRODUCT_MASK
mov w2, #PRR_PRODUCT_D3
cmp w1, w2
beq 4f
beq 5f
and w1, w1, #PRR_PRODUCT_MASK
mov w2, #PRR_PRODUCT_E3
cmp w1, w2
bne 5f
bne 4f
/* When SSCG(MD12) on (E3) */
ldr x1, =RST_MODEMR
ldr w1, [x1]
and w1, w1, #MODEMR_MD12
mov w2, #MODEMR_MD12
cmp w1, w2
bne 5f
bne 4f
/* When SSCG(MD12) on (E3) */
mov w1, #SCBRR_115200BPS_E3_SSCG
b 2f
5:
mov w1, #SCBRR_115200BPS
/* In case of D3 */
ldr x1, =RST_MODEMR
ldr w1, [x1]
and w1, w1, #MODEMR_MD12
mov w2, #MODEMR_MD12
cmp w1, w2
bne 4f
/* When SSCG(MD12) on (D3) */
mov w1, #SCBRR_115200BPS_D3_SSCG
b 2f
4:
mov w1, #SCBRR_115200BPSON
/* In case of H3/M3/M3N or when SSCG(MD12) is off in E3/D3 */
mov w1, #SCBRR_115200BPS
b 2f
3:
mov w1, #SCBRR_230400BPS

2
plat/renesas/rcar/bl2_plat_setup.c
View file

@ -916,7 +916,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
}
if (product == PRR_PRODUCT_E3) {
if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) {
reg = mmio_read_32(RCAR_MODEMR);
sscg = reg & RCAR_SSCG_MASK;
str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;