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fix(gpt): correct the GPC enable sequence

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Since GPC control register fields are permitted to be cached in a TLB,
invalidate TLB after setting fields to ensure future checks are using
the updated values.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I95630b40b673363bbf74da2705deca03089fff3a
This commit is contained in:
Kathleen Capella 2022-07-22 16:26:36 -04:00
parent 1631f9c75c
commit 14cddd7a58
1 changed files with 9 additions and 4 deletions
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13
lib/gpt_rme/gpt_rme.c
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@ -693,10 +693,6 @@ int gpt_enable(void)
return -EPERM; return -EPERM;
} }
/* Invalidate any stale TLB entries */
tlbipaallos();
dsb();
/* Write the base address of the L0 tables into GPTBR */ /* Write the base address of the L0 tables into GPTBR */
write_gptbr_el3(((gpt_config.plat_gpt_l0_base >> GPTBR_BADDR_VAL_SHIFT) write_gptbr_el3(((gpt_config.plat_gpt_l0_base >> GPTBR_BADDR_VAL_SHIFT)
>> GPTBR_BADDR_SHIFT) & GPTBR_BADDR_MASK); >> GPTBR_BADDR_SHIFT) & GPTBR_BADDR_MASK);
@ -718,6 +714,15 @@ int gpt_enable(void)
gpccr_el3 |= SET_GPCCR_ORGN(GPCCR_ORGN_WB_RA_WA); gpccr_el3 |= SET_GPCCR_ORGN(GPCCR_ORGN_WB_RA_WA);
gpccr_el3 |= SET_GPCCR_IRGN(GPCCR_IRGN_WB_RA_WA); gpccr_el3 |= SET_GPCCR_IRGN(GPCCR_IRGN_WB_RA_WA);
/* Prepopulate GPCCR_EL3 but don't enable GPC yet */
write_gpccr_el3(gpccr_el3);
isb();
/* Invalidate any stale TLB entries and any cached register fields */
tlbipaallos();
dsb();
isb();
/* Enable GPT */ /* Enable GPT */
gpccr_el3 |= GPCCR_GPC_BIT; gpccr_el3 |= GPCCR_GPC_BIT;