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feat(tc): add dts entries for MCN PMU nodes

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TC3 has 4 MCN instances, each of them have PMU registers to count
different MCN cache access events, add entries for MCN PMU so that Linux
MCN PMU perf driver can be used with perf.

Change-Id: I7e0ac5025231c3f19d5291292d4cae186accc544
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
This commit is contained in:
Jagdish Gediya 2023-12-18 09:31:57 +00:00 • committed by Leo Yan
parent adc91a3440
commit 1401a42c95
2 changed files with 24 additions and 0 deletions
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20
fdts/tc3.dts
View file

@ -72,6 +72,26 @@
<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
cs-pmu@0 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
};
cs-pmu@1 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
};
cs-pmu@2 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
};
cs-pmu@3 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
};
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";

4
plat/arm/board/tc/include/platform_def.h
View file

@ -422,11 +422,15 @@
#endif /* TARGET_FLAVOUR_FPGA */
#define MCN_OFFSET_IN_NCI 0x00C90000
#define MCN_BASE_ADDR (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI)
#define MCN_PMU_OFFSET 0x000C4000
#define MCN_MICROARCH_OFFSET 0x000E4000
#define MCN_MICROARCH_BASE_ADDR (MCN_BASE_ADDR + MCN_MICROARCH_OFFSET)
#define MCN_SCR_OFFSET 0x4
#define MCN_SCR_PMU_BIT 10
#define MCN_INSTANCES 4
#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \
(n * MCN_ADDRESS_SPACE_SIZE) + \
MCN_PMU_OFFSET)
#endif /* TARGET_PLATFORM == 3 */
#endif /* PLATFORM_DEF_H */