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fix(rcar3-drivers): update DDR setting

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Update R-Car H3/M3/M3N DDR setting rev.0.42.

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ia66dd2329ab3a3ca39132a737e92b3a4864db02d
This commit is contained in:
Yoshifumi Hosoya 2022-07-22 13:04:36 +09:00 • committed by Marek Vasut
parent 69c371bc16
commit 138ddcbf4d
5 changed files with 33 additions and 18 deletions
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17
drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2021, Renesas Electronics Corporation.
* Copyright (c) 2015-2023, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -1180,6 +1180,11 @@ static void regif_pll_wa(void)
ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_LP4_BOOT_TOP_PLL_CTRL
));
if (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_LOW_FREQ_SEL)) {
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_LOW_FREQ_SEL),
_cnf_DDR_PHY_ADR_G_REGSET[0x7f & ddr_regdef_adr(
_reg_PHY_LP4_BOOT_LOW_FREQ_SEL)]);
}
}
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
@ -2856,6 +2861,16 @@ static uint32_t pll3_freq(uint32_t on)
timeout = wait_freqchgreq(1);
if ((!((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))) && (on)) {
if (((1600U * ddr_mbpsdiv) < ddr_mbps) || (prr_product == PRR_PRODUCT_M3)) {
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 0x01421142U);
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 0x00000142U);
} else {
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 0x03421342U);
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 0x00000342U);
}
}
if (timeout) {
return 1;
}

4
drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
View file

@ -1,11 +1,11 @@
/*
* Copyright (c) 2015-2021, Renesas Electronics Corporation.
* Copyright (c) 2015-2023, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define RCAR_DDR_VERSION "rev.0.41"
#define RCAR_DDR_VERSION "rev.0.42"
#define DRAM_CH_CNT 0x04
#define SLICE_CNT 0x04
#define CS_CNT 0x02

12
drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
* Copyright (c) 2015-2023, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -230,8 +230,8 @@ static const uint32_t
/*0693*/ 0x00000000,
/*0694*/ 0x00000000,
/*0695*/ 0x00005064,
/*0696*/ 0x01421142,
/*0697*/ 0x00000142,
/*0696*/ 0x05421542,
/*0697*/ 0x00000542,
/*0698*/ 0x00000000,
/*0699*/ 0x000f1100,
/*069a*/ 0x0f110f11,
@ -240,12 +240,12 @@ static const uint32_t
/*069d*/ 0x0002c000,
/*069e*/ 0x02c002c0,
/*069f*/ 0x000002c0,
/*06a0*/ 0x03421342,
/*06a1*/ 0x00000342,
/*06a0*/ 0x05421542,
/*06a1*/ 0x00000542,
/*06a2*/ 0x00000000,
/*06a3*/ 0x00000000,
/*06a4*/ 0x05020000,
/*06a5*/ 0x14000000,
/*06a5*/ 0x14000001,
/*06a6*/ 0x027f6e00,
/*06a7*/ 0x047f027f,
/*06a8*/ 0x00027f6e,

6
drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
* Copyright (c) 2015-2023, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -210,8 +210,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
/*0b8b*/ 0x01010100,
/*0b8c*/ 0x00000600,
/*0b8d*/ 0x50640000,
/*0b8e*/ 0x01421142,
/*0b8f*/ 0x00000142,
/*0b8e*/ 0x03421342,
/*0b8f*/ 0x00000342,
/*0b90*/ 0x00000000,
/*0b91*/ 0x000f1600,
/*0b92*/ 0x0f160f16,

12
drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation.
* Copyright (c) 2015-2023, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -230,8 +230,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
/*0b93*/ 0x00000000,
/*0b94*/ 0x00000000,
/*0b95*/ 0x00005064,
/*0b96*/ 0x01421142,
/*0b97*/ 0x00000142,
/*0b96*/ 0x05421542,
/*0b97*/ 0x00000542,
/*0b98*/ 0x00000000,
/*0b99*/ 0x000f1600,
/*0b9a*/ 0x0f160f16,
@ -241,12 +241,12 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
/*0b9e*/ 0x02c002c0,
/*0b9f*/ 0x000002c0,
/*0ba0*/ 0x08040201,
/*0ba1*/ 0x03421342,
/*0ba2*/ 0x00000342,
/*0ba1*/ 0x05421542,
/*0ba2*/ 0x00000542,
/*0ba3*/ 0x00000000,
/*0ba4*/ 0x00000000,
/*0ba5*/ 0x05030000,
/*0ba6*/ 0x00010700,
/*0ba6*/ 0x00010701,
/*0ba7*/ 0x00000014,
/*0ba8*/ 0x00027f6e,
/*0ba9*/ 0x047f027f,