Workaround for Neoverse N1 erratum 1262888

Neoverse N1 erratum 1262888 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

docs/design/cpu-specific-build-macros.rst

@@ -249,6 +249,9 @@ For Neoverse N1, the following errata build flags are defined :
 -  ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1
    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
 
+-  ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
 -  ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
 

include/lib/cpus/aarch64/neoverse_n1.h

@@ -31,6 +31,7 @@
 #define NEOVERSE_N1_CPUECTLR_EL1	S3_0_C15_C1_4
 
 #define NEOVERSE_N1_WS_THR_L2_MASK	(ULL(3) << 24)
+#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT	(ULL(1) << 51)
 
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.

lib/cpus/aarch64/neoverse_n1.S

@@ -265,6 +265,33 @@ func check_errata_1262606
 	b	cpu_rev_var_ls
 endfunc check_errata_1262606
 
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1262888
+ * This applies to revision <=r3p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1262888_wa
+	/* Compare x0 against revision r3p0 */
+	mov	x17, x30
+	bl	check_errata_1262888
+	cbz	x0, 1f
+	mrs	x1, NEOVERSE_N1_CPUECTLR_EL1
+	orr	x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
+	msr	NEOVERSE_N1_CPUECTLR_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_n1_1262888_wa
+
+func check_errata_1262888
+	/* Applies to <=r3p0 */
+	mov	x1, #0x30
+	b	cpu_rev_var_ls
+endfunc check_errata_1262888
+
 /* --------------------------------------------------
  * Errata Workaround for Neoverse N1 Erratum 1315703.
  * This applies to revision <= r3p0 of Neoverse N1.
@@ -348,6 +375,11 @@ func neoverse_n1_reset_func
 	bl	errata_n1_1262606_wa
 #endif
 
+#if ERRATA_N1_1262888
+	mov	x0, x18
+	bl	errata_n1_1262888_wa
+#endif
+
 #if ERRATA_N1_1315703
 	mov	x0, x18
 	bl	errata_n1_1315703_wa
@@ -417,6 +449,7 @@ func neoverse_n1_errata_report
 	report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
 	report_errata ERRATA_N1_1257314, neoverse_n1, 1257314
 	report_errata ERRATA_N1_1262606, neoverse_n1, 1262606
+	report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
 	report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
 	report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
 

lib/cpus/cpu-ops.mk

@@ -266,6 +266,10 @@ ERRATA_N1_1257314	?=0
 # only to revision <= r3p0 of the Neoverse N1 cpu.
 ERRATA_N1_1262606	?=0
 
+# Flag to apply erratum 1262888 workaround during reset. This erratum applies
+# only to revision <= r3p0 of the Neoverse N1 cpu.
+ERRATA_N1_1262888	?=0
+
 # Flag to apply erratum 1315703 workaround during reset. This erratum applies
 # to revisions before r3p1 of the Neoverse N1 cpu.
 ERRATA_N1_1315703	?=1
@@ -487,6 +491,10 @@ $(eval $(call add_define,ERRATA_N1_1257314))
 $(eval $(call assert_boolean,ERRATA_N1_1262606))
 $(eval $(call add_define,ERRATA_N1_1262606))
 
+# Process ERRATA_N1_1262888 flag
+$(eval $(call assert_boolean,ERRATA_N1_1262888))
+$(eval $(call add_define,ERRATA_N1_1262888))
+
 # Process ERRATA_N1_1315703 flag
 $(eval $(call assert_boolean,ERRATA_N1_1315703))
 $(eval $(call add_define,ERRATA_N1_1315703))