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locks: bakery: use is_dcache_enabled() helper
bakery_lock_normal.c uses the raw register accessor, read_sctlr(_el3) to check whether the dcache is enabled. Using is_dcache_enabled() is cleaner, and a good abstraction for the library code like this. A problem is is_dcache_enabled() is declared in the local header, lib/xlat_tables_v2/xlat_tables_private.h I searched for a good place to declare this helper. Moving it to arch_helpers.h, closed to cache operation helpers, looks good enough to me. I also changed the type of 'is_cached' to bool for consistency, and to avoid MISRA warnings. Change-Id: I9b016f67bc8eade25c316aa9c0db0fa4cd375b79 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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4 changed files with 12 additions and 19 deletions
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -8,6 +8,7 @@
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#define ARCH_HELPERS_H
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#define ARCH_HELPERS_H
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#include <cdefs.h>
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#include <cdefs.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdint.h>
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#include <string.h>
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#include <string.h>
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@ -178,6 +179,7 @@ static inline void _op ## _type(u_register_t v) \
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void flush_dcache_range(uintptr_t addr, size_t size);
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void flush_dcache_range(uintptr_t addr, size_t size);
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void clean_dcache_range(uintptr_t addr, size_t size);
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void clean_dcache_range(uintptr_t addr, size_t size);
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void inv_dcache_range(uintptr_t addr, size_t size);
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void inv_dcache_range(uintptr_t addr, size_t size);
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bool is_dcache_enabled(void);
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void dcsw_op_louis(u_register_t op_type);
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void dcsw_op_louis(u_register_t op_type);
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void dcsw_op_all(u_register_t op_type);
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void dcsw_op_all(u_register_t op_type);
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@ -226,6 +226,7 @@ DEFINE_SYSOP_PARAM_FUNC(xpaci)
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void flush_dcache_range(uintptr_t addr, size_t size);
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void flush_dcache_range(uintptr_t addr, size_t size);
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void clean_dcache_range(uintptr_t addr, size_t size);
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void clean_dcache_range(uintptr_t addr, size_t size);
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void inv_dcache_range(uintptr_t addr, size_t size);
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void inv_dcache_range(uintptr_t addr, size_t size);
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bool is_dcache_enabled(void);
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void dcsw_op_louis(u_register_t op_type);
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void dcsw_op_louis(u_register_t op_type);
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void dcsw_op_all(u_register_t op_type);
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void dcsw_op_all(u_register_t op_type);
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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@ -84,7 +84,7 @@ static inline void read_cache_op(uintptr_t addr, bool cached)
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/* Helper function to check if the lock is acquired */
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/* Helper function to check if the lock is acquired */
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static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info,
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static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info,
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int is_cached)
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bool is_cached)
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{
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{
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/*
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/*
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* Even though lock data is updated only by the owning cpu and
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* Even though lock data is updated only by the owning cpu and
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@ -99,7 +99,7 @@ static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info,
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}
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}
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static unsigned int bakery_get_ticket(bakery_lock_t *lock,
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static unsigned int bakery_get_ticket(bakery_lock_t *lock,
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unsigned int me, int is_cached)
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unsigned int me, bool is_cached)
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{
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{
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unsigned int my_ticket, their_ticket;
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unsigned int my_ticket, their_ticket;
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unsigned int they;
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unsigned int they;
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@ -164,17 +164,14 @@ static unsigned int bakery_get_ticket(bakery_lock_t *lock,
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void bakery_lock_get(bakery_lock_t *lock)
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void bakery_lock_get(bakery_lock_t *lock)
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{
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{
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unsigned int they, me, is_cached;
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unsigned int they, me;
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unsigned int my_ticket, my_prio, their_ticket;
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unsigned int my_ticket, my_prio, their_ticket;
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bakery_info_t *their_bakery_info;
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bakery_info_t *their_bakery_info;
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unsigned int their_bakery_data;
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unsigned int their_bakery_data;
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bool is_cached;
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me = plat_my_core_pos();
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me = plat_my_core_pos();
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#ifdef __aarch64__
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is_cached = is_dcache_enabled();
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is_cached = read_sctlr_el3() & SCTLR_C_BIT;
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#else
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is_cached = read_sctlr() & SCTLR_C_BIT;
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#endif
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/* Get a ticket */
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/* Get a ticket */
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my_ticket = bakery_get_ticket(lock, me, is_cached);
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my_ticket = bakery_get_ticket(lock, me, is_cached);
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@ -232,11 +229,7 @@ void bakery_lock_get(bakery_lock_t *lock)
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void bakery_lock_release(bakery_lock_t *lock)
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void bakery_lock_release(bakery_lock_t *lock)
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{
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{
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bakery_info_t *my_bakery_info;
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bakery_info_t *my_bakery_info;
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#ifdef __aarch64__
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bool is_cached = is_dcache_enabled();
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unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT;
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#else
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unsigned int is_cached = read_sctlr() & SCTLR_C_BIT;
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#endif
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my_bakery_info = get_bakery_info(plat_my_core_pos(), lock);
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my_bakery_info = get_bakery_info(plat_my_core_pos(), lock);
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -99,9 +99,6 @@ unsigned long long xlat_arch_get_max_supported_pa(void);
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*/
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*/
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bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx);
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bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx);
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/* Returns true if the data cache is enabled at the current EL. */
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bool is_dcache_enabled(void);
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/*
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/*
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* Returns minimum virtual address space size supported by the architecture
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* Returns minimum virtual address space size supported by the architecture
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*/
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*/
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