Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-18 02:24:18 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge changes from topic "sm/err_errata" into integration

Browse source 
* changes:
  fix(cpus): fix the rev-var of Neoverse-V1
  fix(errata-abi): update the Neoverse-N2 errata ABI struct
  fix(errata-abi): update the neoverse-N1 errata ABI struct
  fix(cpus): fix the rev-var of Cortex-X2
  fix(errata-abi): update the Cortex-A78C errata ABI struct
  fix(cpus): update the rev-var for Cortex-A78AE
  fix(errata-abi): update the Cortex-A76 errata ABI struct
  fix(cpus): fix the rev-var for Cortex-A710
This commit is contained in:
Lauren Wehrmeister 2023-10-26 21:03:06 +02:00 • committed by TrustedFirmware Code Review
commit 113273aac4
7 changed files with 67 additions and 59 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
docs/design/cpu-specific-build-macros.rst
View file

@ -335,26 +335,26 @@ For Cortex-A78, the following errata build flags are defined :
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
it is still open.
For Cortex-A78 AE, the following errata build flags are defined :
For Cortex-A78AE, the following errata build flags are defined :
- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
This erratum is still open.
- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
erratum is still open.
- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
erratum is still open.
Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
This erratum is still open.
- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
erratum is still open.
- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to
Cortex-A78 AE CPU. This erratum affects system configurations that do not use
Cortex-A78AE CPU. This erratum affects system configurations that do not use
an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and
r0p2. This erratum is still open.
@ -498,7 +498,8 @@ For Neoverse V1, the following errata build flags are defined :
revision. It is still open.
- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1
CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of
the CPU.
- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1
CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
@ -572,7 +573,7 @@ For Cortex-A710, the following errata build flags are defined :
- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is still open.
and r2p1 of the CPU and is still open.
- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
@ -685,7 +686,7 @@ For Cortex-X2, the following errata build flags are defined :
it is still open.
- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2
CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU,
it is still open.
- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2

4
lib/cpus/aarch64/cortex_a710.S
View file

@ -80,14 +80,14 @@ workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002
sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46
workaround_reset_end cortex_a710, ERRATUM(2055002)
check_erratum_ls cortex_a710, ERRATUM(2055002), CPU_REV(2, 0)
check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0)
workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056
sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \
CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH
workaround_reset_end cortex_a710, ERRATUM(2058056)
check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 0)
check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1)
workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180
ldr x0,=0x3

2
lib/cpus/aarch64/cortex_a78_ae.S
View file

@ -70,7 +70,7 @@ workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748
sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0
workaround_reset_end cortex_a78_ae, ERRATUM(2376748)
check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 1)
check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 2)
workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408
/* --------------------------------------------------------

2
lib/cpus/aarch64/cortex_x2.S
View file

@ -50,7 +50,7 @@ workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056
CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
workaround_reset_end cortex_x2, ERRATUM(2058056)
check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 0)
check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1)
workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180
/* Apply instruction patching sequence */

4
lib/cpus/aarch64/neoverse_v1.S
View file

@ -161,7 +161,7 @@ workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267
msr NEOVERSE_V1_CPUECTLR_EL1, x1
workaround_reset_end neoverse_v1, ERRATUM(2108267)
check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 1)
check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 2)
workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242
mov x0, #0x3
@ -194,7 +194,7 @@ workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912
sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0
workaround_reset_end neoverse_v1, ERRATUM(2294912)
check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 1)
check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 2)
workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203
/* Set bit 40 in ACTLR2_EL1 */

9
lib/cpus/cpu-ops.mk
View file

@ -352,7 +352,7 @@ CPU_FLAG_LIST += ERRATA_A78_AE_1941500
CPU_FLAG_LIST += ERRATA_A78_AE_1951502
# Flag to apply erratum 2376748 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
# to revisions r0p0, r0p1 and r0p2 of the A78 AE cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78_AE_2376748
# Flag to apply erratum 2395408 workaround during reset. This erratum applies
@ -517,7 +517,7 @@ CPU_FLAG_LIST += ERRATA_V1_2108267
CPU_FLAG_LIST += ERRATA_V1_2216392
# Flag to apply erratum 2294912 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
# to revisions r0p0, r1p0, and r1p1 and r1p2 of the Neoverse V1 cpu and is still open.
CPU_FLAG_LIST += ERRATA_V1_2294912
# Flag to apply erratum 2372203 workaround during reset. This erratum applies
@ -557,7 +557,8 @@ CPU_FLAG_LIST += ERRATA_A710_2081180
CPU_FLAG_LIST += ERRATA_A710_2083908
# Flag to apply erratum 2058056 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is still
# open.
CPU_FLAG_LIST += ERRATA_A710_2058056
# Flag to apply erratum 2055002 workaround during reset. This erratum applies
@ -689,7 +690,7 @@ CPU_FLAG_LIST += ERRATA_N2_2779511
CPU_FLAG_LIST += ERRATA_X2_2002765
# Flag to apply erratum 2058056 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X2_2058056
# Flag to apply erratum 2083908 workaround during reset. This erratum applies

84
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -163,10 +163,12 @@ struct em_cpu_list cpu_list[] = {
[5] = {1262606, 0x00, 0x30, ERRATA_A76_1262606},
[6] = {1262888, 0x00, 0x30, ERRATA_A76_1262888},
[7] = {1275112, 0x00, 0x30, ERRATA_A76_1275112},
[8] = {1791580, 0x00, 0x40, ERRATA_A76_1791580},
[9] = {1868343, 0x00, 0x40, ERRATA_A76_1868343},
[10] = {1946160, 0x30, 0x41, ERRATA_A76_1946160},
[11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[8] = {1286807, 0x00, 0x30, ERRATA_A76_1286807},
[9] = {1791580, 0x00, 0x40, ERRATA_A76_1791580},
[10] = {1868343, 0x00, 0x40, ERRATA_A76_1868343},
[11] = {1946160, 0x30, 0x41, ERRATA_A76_1946160},
[12] = {2743102, 0x00, 0x41, ERRATA_A76_2743102},
[13 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A76_H_INC */
@ -216,7 +218,7 @@ struct em_cpu_list cpu_list[] = {
.cpu_errata_list = {
[0] = {1941500, 0x00, 0x01, ERRATA_A78_AE_1941500},
[1] = {1951502, 0x00, 0x01, ERRATA_A78_AE_1951502},
[2] = {2376748, 0x00, 0x01, ERRATA_A78_AE_2376748},
[2] = {2376748, 0x00, 0x02, ERRATA_A78_AE_2376748},
[3] = {2395408, 0x00, 0x01, ERRATA_A78_AE_2395408},
[4] = {2712574, 0x00, 0x02, ERRATA_A78_AE_2712574, \
ERRATA_NON_ARM_INTERCONNECT},
@ -229,15 +231,17 @@ struct em_cpu_list cpu_list[] = {
{
.cpu_partnumber = CORTEX_A78C_MIDR,
.cpu_errata_list = {
[0] = {2132064, 0x01, 0x02, ERRATA_A78C_2132064},
[1] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638},
[2] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749},
[3] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411},
[4] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
[0] = {1827430, 0x00, 0x00, ERRATA_A78C_1827430},
[1] = {1827440, 0x00, 0x00, ERRATA_A78C_1827440},
[2] = {2132064, 0x01, 0x02, ERRATA_A78C_2132064},
[3] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638},
[4] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749},
[5] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411},
[6] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
ERRATA_NON_ARM_INTERCONNECT},
[5] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
[6] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
[7 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[7] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
[8] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
[9 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A78C_H_INC */
@ -258,21 +262,22 @@ struct em_cpu_list cpu_list[] = {
{
.cpu_partnumber = NEOVERSE_N1_MIDR,
.cpu_errata_list = {
[0] = {1073348, 0x00, 0x10, ERRATA_N1_1073348},
[1] = {1130799, 0x00, 0x20, ERRATA_N1_1130799},
[2] = {1165347, 0x00, 0x20, ERRATA_N1_1165347},
[3] = {1207823, 0x00, 0x20, ERRATA_N1_1207823},
[4] = {1220197, 0x00, 0x20, ERRATA_N1_1220197},
[5] = {1257314, 0x00, 0x30, ERRATA_N1_1257314},
[6] = {1262606, 0x00, 0x30, ERRATA_N1_1262606},
[7] = {1262888, 0x00, 0x30, ERRATA_N1_1262888},
[8] = {1275112, 0x00, 0x30, ERRATA_N1_1275112},
[9] = {1315703, 0x00, 0x30, ERRATA_N1_1315703},
[10] = {1542419, 0x30, 0x40, ERRATA_N1_1542419},
[11] = {1868343, 0x00, 0x40, ERRATA_N1_1868343},
[12] = {1946160, 0x30, 0x41, ERRATA_N1_1946160},
[13] = {2743102, 0x00, 0x41, ERRATA_N1_2743102},
[14 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[0] = {1043202, 0x00, 0x10, ERRATA_N1_1043202},
[1] = {1073348, 0x00, 0x10, ERRATA_N1_1073348},
[2] = {1130799, 0x00, 0x20, ERRATA_N1_1130799},
[3] = {1165347, 0x00, 0x20, ERRATA_N1_1165347},
[4] = {1207823, 0x00, 0x20, ERRATA_N1_1207823},
[5] = {1220197, 0x00, 0x20, ERRATA_N1_1220197},
[6] = {1257314, 0x00, 0x30, ERRATA_N1_1257314},
[7] = {1262606, 0x00, 0x30, ERRATA_N1_1262606},
[8] = {1262888, 0x00, 0x30, ERRATA_N1_1262888},
[9] = {1275112, 0x00, 0x30, ERRATA_N1_1275112},
[10] = {1315703, 0x00, 0x30, ERRATA_N1_1315703},
[11] = {1542419, 0x30, 0x40, ERRATA_N1_1542419},
[12] = {1868343, 0x00, 0x40, ERRATA_N1_1868343},
[13] = {1946160, 0x30, 0x41, ERRATA_N1_1946160},
[14] = {2743102, 0x00, 0x41, ERRATA_N1_2743102},
[15 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_N1_H_INC */
@ -281,23 +286,24 @@ struct em_cpu_list cpu_list[] = {
{
.cpu_partnumber = NEOVERSE_V1_MIDR,
.cpu_errata_list = {
[0] = {1618635, 0x00, 0x0F, ERRATA_V1_1618635},
[0] = {1618635, 0x00, 0x00, ERRATA_V1_1618635},
[1] = {1774420, 0x00, 0x10, ERRATA_V1_1774420},
[2] = {1791573, 0x00, 0x10, ERRATA_V1_1791573},
[3] = {1852267, 0x00, 0x10, ERRATA_V1_1852267},
[4] = {1925756, 0x00, 0x11, ERRATA_V1_1925756},
[5] = {1940577, 0x10, 0x11, ERRATA_V1_1940577},
[6] = {1966096, 0x10, 0x11, ERRATA_V1_1966096},
[7] = {2108267, 0x00, 0x11, ERRATA_V1_2108267},
[7] = {2108267, 0x00, 0x12, ERRATA_V1_2108267},
[8] = {2139242, 0x00, 0x11, ERRATA_V1_2139242},
[9] = {2216392, 0x10, 0x11, ERRATA_V1_2216392},
[10] = {2294912, 0x00, 0x11, ERRATA_V1_2294912},
[10] = {2294912, 0x00, 0x12, ERRATA_V1_2294912},
[11] = {2372203, 0x00, 0x11, ERRATA_V1_2372203},
[12] = {2701953, 0x00, 0x11, ERRATA_V1_2701953, \
ERRATA_NON_ARM_INTERCONNECT},
[13] = {2743093, 0x00, 0x12, ERRATA_V1_2743093},
[14] = {2779461, 0x00, 0x12, ERRATA_V1_2779461},
[15 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[14] = {2743233, 0x00, 0x12, ERRATA_V1_2743233},
[15] = {2779461, 0x00, 0x12, ERRATA_V1_2779461},
[16 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_V1_H_INC */
@ -310,7 +316,7 @@ struct em_cpu_list cpu_list[] = {
[1] = {2008768, 0x00, 0x20, ERRATA_A710_2008768},
[2] = {2017096, 0x00, 0x20, ERRATA_A710_2017096},
[3] = {2055002, 0x10, 0x20, ERRATA_A710_2055002},
[4] = {2058056, 0x00, 0x20, ERRATA_A710_2058056},
[4] = {2058056, 0x00, 0x21, ERRATA_A710_2058056},
[5] = {2081180, 0x00, 0x20, ERRATA_A710_2081180},
[6] = {2083908, 0x20, 0x20, ERRATA_A710_2083908},
[7] = {2136059, 0x00, 0x20, ERRATA_A710_2136059},
@ -336,7 +342,7 @@ struct em_cpu_list cpu_list[] = {
[1] = {2009478, 0x00, 0x00, ERRATA_N2_2009478},
[2] = {2025414, 0x00, 0x00, ERRATA_N2_2025414},
[3] = {2067956, 0x00, 0x00, ERRATA_N2_2067956},
[4] = {2138953, 0x00, 0x00, ERRATA_N2_2138953},
[4] = {2138953, 0x00, 0x03, ERRATA_N2_2138953},
[5] = {2138956, 0x00, 0x00, ERRATA_N2_2138956},
[6] = {2138958, 0x00, 0x00, ERRATA_N2_2138958},
[7] = {2189731, 0x00, 0x00, ERRATA_N2_2189731},
@ -344,7 +350,7 @@ struct em_cpu_list cpu_list[] = {
[9] = {2242415, 0x00, 0x00, ERRATA_N2_2242415},
[10] = {2280757, 0x00, 0x00, ERRATA_N2_2280757},
[11] = {2326639, 0x00, 0x00, ERRATA_N2_2326639},
[12] = {2376738, 0x00, 0x00, ERRATA_N2_2376738},
[12] = {2376738, 0x00, 0x03, ERRATA_N2_2376738},
[13] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
[14] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
ERRATA_NON_ARM_INTERCONNECT},
@ -362,13 +368,13 @@ struct em_cpu_list cpu_list[] = {
.cpu_errata_list = {
[0] = {2002765, 0x00, 0x20, ERRATA_X2_2002765},
[1] = {2017096, 0x00, 0x20, ERRATA_X2_2017096},
[2] = {2058056, 0x00, 0x20, ERRATA_X2_2058056},
[2] = {2058056, 0x00, 0x21, ERRATA_X2_2058056},
[3] = {2081180, 0x00, 0x20, ERRATA_X2_2081180},
[4] = {2083908, 0x00, 0x20, ERRATA_X2_2083908},
[4] = {2083908, 0x20, 0x20, ERRATA_X2_2083908},
[5] = {2147715, 0x20, 0x20, ERRATA_X2_2147715},
[6] = {2216384, 0x00, 0x20, ERRATA_X2_2216384},
[7] = {2282622, 0x00, 0x21, ERRATA_X2_2282622},
[8] = {2371105, 0x00, 0x21, ERRATA_X2_2371105},
[8] = {2371105, 0x00, 0x20, ERRATA_X2_2371105},
[9] = {2701952, 0x00, 0x21, ERRATA_X2_2701952, \
ERRATA_NON_ARM_INTERCONNECT},
[10] = {2768515, 0x00, 0x21, ERRATA_X2_2768515},