From 1f732471320cee7b4f355ecff7dcfab7018e48ae Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Tue, 27 Feb 2024 17:34:05 -0600 Subject: [PATCH 1/2] fix(cpus): workaround for Cortex-A715 erratum 2420947 Cortex-A715 erratum 2420947 is a cat B erratum that applies only to revision r1p0 and is fixed in r1p1. The workaround is to set bit[33] of CPUACTLR2_EL1. This will prevent store and store-release to merge inside the write buffer, and it is not expected to have much performance impacts. SDEN can be found here: https://developer.arm.com/documentation/SDEN2148827/latest Change-Id: I01a71b878cd958e742ff8357f8cdfbfc5625de47 Signed-off-by: Bipin Ravi --- docs/design/cpu-specific-build-macros.rst | 4 ++++ lib/cpus/aarch64/cortex_a715.S | 6 ++++++ lib/cpus/cpu-ops.mk | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 9aaa07896..416f9eefa 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -881,6 +881,10 @@ For Cortex-A520, the following errata build flags are defined : For Cortex-A715, the following errata build flags are defined : +- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to + Cortex-A715 CPU. This needs to be enabled only for revision r1p0. + It is fixed in r1p1. + - ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no workaround for revision r0p0. It is fixed in r1p1. diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S index 44796b6f0..a9bb370c0 100644 --- a/lib/cpus/aarch64/cortex_a715.S +++ b/lib/cpus/aarch64/cortex_a715.S @@ -26,6 +26,12 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 #endif /* WORKAROUND_CVE_2022_23960 */ +workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947 + sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33) +workaround_reset_end cortex_a715, ERRATUM(2420947) + +check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0) + workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27) workaround_reset_end cortex_a715, ERRATUM(2429384) diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 5e68ddab7..5bdd9e409 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -911,6 +911,10 @@ CPU_FLAG_LIST += ERRATA_V2_2779510 # This erratum applies to revisions r0p0, r0p1. Fixed in r0p2. CPU_FLAG_LIST += ERRATA_V2_2801372 +# Flag to apply erratum 2420947 workaround during reset. This erratum applies +# only to revision r1p0. It is fixed in r1p1. +CPU_FLAG_LIST += ERRATA_A715_2420947 + # Flag to apply erratum 2429384 workaround during reset. This erratum applies # to revision r1p0. There is no workaround for r0p0. It is fixed in r1p1. CPU_FLAG_LIST += ERRATA_A715_2429384 From 53b3cd2532dbdb794ddfedcc8a3985d2404eb6f7 Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Tue, 27 Feb 2024 17:49:12 -0600 Subject: [PATCH 2/2] fix(cpus): workaround for Cortex-A715 erratum 2331818 Cortex-A715 erratum 2331818 is a cat B erratum that applies to revisions r0p0 and r1p0 and is fixed in r1p1. The workaround is to set bit[20] of CPUACTLR2_EL1. Setting this bit is expected to have a negligible performance impact. SDEN can be found here: https://developer.arm.com/documentation/SDEN2148827/latest Change-Id: If3b1ed78b145ab6515cdd41135314350ed556381 Signed-off-by: Bipin Ravi --- docs/design/cpu-specific-build-macros.rst | 4 ++++ lib/cpus/aarch64/cortex_a715.S | 6 ++++++ lib/cpus/cpu-ops.mk | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 416f9eefa..6f5f01f5b 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -881,6 +881,10 @@ For Cortex-A520, the following errata build flags are defined : For Cortex-A715, the following errata build flags are defined : +- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to + Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. + It is fixed in r1p1. + - ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to Cortex-A715 CPU. This needs to be enabled only for revision r1p0. It is fixed in r1p1. diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S index a9bb370c0..65f3c0400 100644 --- a/lib/cpus/aarch64/cortex_a715.S +++ b/lib/cpus/aarch64/cortex_a715.S @@ -26,6 +26,12 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 #endif /* WORKAROUND_CVE_2022_23960 */ +workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818 + sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) +workaround_reset_end cortex_a715, ERRATUM(2331818) + +check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0) + workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33) workaround_reset_end cortex_a715, ERRATUM(2420947) diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 5bdd9e409..1c0b09212 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -911,6 +911,10 @@ CPU_FLAG_LIST += ERRATA_V2_2779510 # This erratum applies to revisions r0p0, r0p1. Fixed in r0p2. CPU_FLAG_LIST += ERRATA_V2_2801372 +# Flag to apply erratum 2331818 workaround during reset. This erratum applies +# to revisions r0p0 and r1p0. It is fixed in r1p1. +CPU_FLAG_LIST += ERRATA_A715_2331818 + # Flag to apply erratum 2420947 workaround during reset. This erratum applies # only to revision r1p0. It is fixed in r1p1. CPU_FLAG_LIST += ERRATA_A715_2420947